PLL520-17 PhaseLink (PLL), PLL520-17 Datasheet - Page 4

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PLL520-17

Manufacturer Part Number
PLL520-17
Description
, 65-130MHz In, 65-800MHz Out, CMOS
Manufacturer
PhaseLink (PLL)
Datasheet
4. General Electrical Specifications
5. Jitter specifications
*: To be measured
6. Phase noise specifications
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Supply Current (Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
Period jitter RMS
Period jitter peak-to-peak
Integrated jitter RMS
Phase Noise relative to
carrier
PARAMETERS
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
PARAMETERS
PARAMETERS
77.76MHz
155.52MHz
622.08MHz
FREQUENCY
77.76MHz
155.52MHz
622.08MHz
77.76MHz
155.52MHz
622.08MHz
Integrated 12 kHz to 20 MHz at 77.76MHz
Integrated 12 kHz to 20 MHz at 155.52MHz
Integrated 12 kHz to 20 MHz at 622.08MHz
SYMBOL
V
I
DD
DD
PECL/LVDS/CMOS
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
@10Hz
CONDITIONS
-75
-75
-75
CONDITIONS
Preliminary
@100Hz
-95
-95
-95
PLL520-17/-18/-19
@1kHz
-125
-120
-115
MIN.
MIN.
3.13
45
45
45
Universal Low Phase Noise IC’s
@10kHz
-145
-125
-118
TYP.
TYP.
3.5*
0.5*
1.5*
1.5*
24*
29*
32*
50
50
50
4*
5*
50
@100kHz
Rev 4/09/02 Page 4
100/80/40
-155
-123
-115
MAX.
MAX.
3.47
55
55
55
UNITS
dBc/Hz
UNITS
UNITS
mA
mA
ps
ps
ps
%
V

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