PLL502-10 PhaseLink (PLL), PLL502-10 Datasheet - Page 2

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PLL502-10

Manufacturer Part Number
PLL502-10
Description
, 12-25MHz In, 750kHz-400MHz Out, CMOS, Pecl, LVDS
Manufacturer
PhaseLink (PLL)
Datasheet
FREQUENCY SELECTION TABLE
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Pad #28
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
SEL3
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Pad #29
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Pad #19
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Pad #20
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Fin / 8
Fin x 2
Reserved
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
Selected Multiplier
Preliminary
PLL502-10
Rev 11/06/02 Page 2

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