ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 89

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

Note
1 t
SSD1908
12
is the delay from when data is placed on the bus until the data is latched into the write buffer.
Symbol
T
f
CLKO
t
t
t
t
CLKO
t
t
t
t
t
t
t
t
t
t
15a
15b
15d
15c
t
t
t
t
t
t
t
t
5a
5b
5c
5d
10
11
12
13
14
16
1
2
3
4
6
7
8
9
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[17:1] setup 1st CLKO when CSX# = 0 and
either UWE#/LWE# or OE# =0
A[16:1] hold from CSX# rising edge
CSX# asserted for MCLK = BCLK
CSX# asserted for MCLK = BCLK ÷2
CSX# asserted for MCLK = BCLK ÷3
CSX# asserted for MCLK = BCLK ÷4
CSX# setup to CLKO rising edge
CSX# rising edge to CLKO rising edge
UWE#/LWE# falling edge to CLKO rising
edge
UWE#/LWE# rising edge to CSX# rising
edge
OE# falling edge to CLKO rising edge
OE# hold from CSX# rising edge
D[15:0] setup to 3rd CLKO when CSX#,
UWE#/LWE# asserted (write cycle) (see
note 1)
D[15:0] hold from CSX# rising edge(write
cycle)
Falling edge of OE# to D[15:0] driven
(read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK (read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷2 (read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷3 (read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷4 (read cycle)
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
Rev 1.0
Table 10-8 : Motorola DragonBall Interface without DTACK# Timing
P 79/79
Parameter
Oct 2003
1/f
Min
28.1
28.1
CLKO
0
0
0
0
0
0
0
1
0
0
3
2
MC68EZ328
Max
13
18
23
28
13
18
23
28
16
15
12
1/f
Min
13.6
13.6
CLKO
0
0
0
0
0
0
1
0
0
0
3
2
MC68VZ328
Solomon Systech
Max
13
18
23
28
13
18
23
28
33
15
12
Units
T
T
T
T
T
T
T
T
MHz
CLKO
CLKO
CLKO
CLKO
CLKO
CLKO
CLKO
CLKO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns