ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 81

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

1. t
SSD1908
11
is the delay from when data is placed on the bus until the data is latched into the write buffer.
Symbol
T
f
t
t
t
t
t
t
t
t
t
t
CLK
t
t
t
t
t
t
t
t
7a
7b
7c
7d
10
11
12
13
14
15
CLK
1
2
3
4
5
6
8
9
Rev 1.0
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[17:1], M/R# setup to first CLK rising edge where CS# = 0 and
either RD0#, RD1# = 0 or WE0#, WE1# = 0
A[17:1], M/R# hold from either RD0#, RD1# or WE0#, WE1#
rising edge
CS# setup to CLK rising edge
CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷3
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷4
RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
driven low
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
high impedance
D[15:0] setup to third CLK rising edge where CS# = 0 and
WE0#,WE1#=0 (write cycle)(see note 1)
D[15:0] hold from WAIT# rising edge (write cycle)
RD0#, RD1# falling edge to D[15:0] driven (read cycle)
WAIT# rising edge to D[15:0] valid (read cycle)
RD0#, RD1# rising edge to D[15:0] high impedance (read cycle)
P 71/71
Table 10-4 : Generic #1 Interface Timing
Oct 2003
Parameter
2
1/f
Min
6
6
1
0
1
1
1
3
3
0
0
3
3
CLK
Solomon Systech
Max
11
66
13
18
23
28
15
13
14
2
Units
T
T
T
T
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK