ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 60

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

Bit 7
Note
For information on GPIO pin mapping when HR-TFT panels are selected, see Table 5-2 : LCD Interface Pin
Descriptions.
Bit 6
Bit 5
Bit 4
Bit 3
Reset
Reset
Type
state
Type
state
Solomon Systech
Bit
Bit
General Purpose IO Pins Configuration Register 1
General Purpose IO Pins Status/Control Register 0
GPIO Pin
Enable
Input
RW
NA
7
0
7
0
0
GPIO6 Pin
IO Status
GPIO Pin Input Enable
This bit is used to enable the input function of the GPIO pins. It must be changed to a 1
after power-on reset to enable the input function of the GPIO pins.
GPIO6 Pin IO Status
When GPIO6 is configured as an output, writing a 1 to this bit drives GPIO6 high and
writing a 0 to this bit drives GPIO6 low.
When GPIO6 is configured as an input, a read from this bit returns the status of
GPIO6.
GPIO5 Pin IO Status
When GPIO5 is configured as an output, writing a 1 to this bit drives GPIO5 high and
writing a 0 to this bit drives GPIO5 low.
When GPIO5 is configured as an input, a read from this bit returns the status of
GPIO5.
GPIO4 Pin IO Status
When GPIO4 is configured as an output, writing a 1 to this bit drives GPIO4 high and
writing a 0 to this bit drives GPIO4 low.
When GPIO4 is configured as an input, a read from this bit returns the status of
GPIO4.
GPIO3 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO3 is
configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this
bit drives GPIO3 low.
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO3 is
configured as an input, a read from this bit returns the status of GPIO3.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal SPL
signal is enabled whatever the value of this bit.
RW
NA
6
0
0
6
0
GPIO5 Pin
IO Status
RW
NA
5
0
0
5
0
GPIO4 Pin
IO Status
RW
NA
4
0
0
4
0
Oct 2003
GPIO3 Pin
IO Status
RW
NA
3
0
0
3
0
P 50/50
GPIO2 Pin
IO Status
RW
NA
2
0
0
2
0
Rev 1.0
GPIO1 Pin
IO Status
RW
NA
1
0
0
1
0
SSD1908
REG[A9h]
REG[ACh]
GPIO0 Pin
IO Status
RW
NA
0
0
0
0
0