PLL103-02D PhaseLink (PLL), PLL103-02D Datasheet - Page 5

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PLL103-02D

Manufacturer Part Number
PLL103-02D
Description
Standard Clock Buffer (SDRAM And DDR) , 12x2 Ddr, 66 - 170MHz in
Manufacturer
PhaseLink (PLL)
Datasheet
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Operating Conditions
3. Electrical Specifications
Note: TBM: To be measured
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
ESD Voltage
Supply Voltage
Input Capacitance
Output Capacitance
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High
Voltage
Output Low
Voltage
Output High
Current
Output Low
Current
PARAMETERS
SYMBOL
PARAMETERS
PARAMETERS
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
V
V
V
I
V
I
I
I
OH
OL
IH
OH
IL
OL
IH
IL
All Inputs except I2C
All inputs except I2C
V
V
IOL = -12mA,
IOL = 12mA,
VDD = 2.375V, VOUT=1V
VDD = 2.375V, VOUT=1.2V
IN
IN
= V
= 0
DD
CONDITIONS
VDD = 2.375V
VDD = 2.375V
SYMBOL
SYMBOL
V
C
V
DD2.5
C
V
T
T
V
OUT
DD
O
IN
S
A
I
PLL103-02 Rev.D
V
MIN.
SS
-18
2.0
1.7
26
-0.3
V
V
V
2.375
MIN.
MIN.
SS
SS
SS
-65
0
-
-
-
0.5
0.5
0.5
TYP.
-32
35
V
V
MAX.
MAX.
DD
DD
2.625
150
7.0
70
2
5
6
V
+
+
MAX.
Rev 01/11/01 Page 5
DD
0.5
0.5
TBM
TBM
0.8
0.6
+0.3
UNITS
UNITS
UNITS
KV
pF
pF
V
V
V
V
mA
mA
C
C
uA
uA
V
V
V
V

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