PLL103-02D PhaseLink (PLL), PLL103-02D Datasheet

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PLL103-02D

Manufacturer Part Number
PLL103-02D
Description
Standard Clock Buffer (SDRAM And DDR) , 12x2 Ddr, 66 - 170MHz in
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
BUF_IN
SDATA
SCLK
Generates 24 output buffer from one input.
Supports up to four DDR DIMMS.
Supports 266MHz DDR SDRAM.
One additional output for feedback.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V Supply range.
Enhanced DDR Output Drive selected by I2C.
Available in 48 pin SSOP.
PD#
Control
I2C
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
DDR0T
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
DDR4C
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
PIN CONFIGURATION
Note: #: Active Low
DESCRIPTIONS
The PLL103-02 Rev.D is designed as a 2.5V buffer
to distribute high-speed clocks in PC applications.
The device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS.
The PLL103-02 Rev.D can be used in conjunction
with the PLL202-04 or similar clock synthesizer for
the VIA Pro 266 chipset.
The PLL103-02 Rev.D also has an I2C interface,
which can enable or disable each output clock.
When power up, all output clocks are enabled (has
internal pull up).
VDD2.5
VDD2.5
VDD2.5
BUF_IN
VDD2.5
VDD2.5
DDR0C
DDR1C
DDR2C
DDR3C
DDR4C
DDR5C
FBOUT
SDATA
DDR0T
DDR1T
DDR2T
DDR3T
DDR4T
DDR5T
GND
GND
GND
GND
PLL103-02 Rev.D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N/C
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PD#
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
Rev 01/11/01 Page 1

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PLL103-02D Summary of contents

Page 1

... Note: #: Active Low DDR2T DDR2C DDR3T DESCRIPTIONS DDR3C DDR4T The PLL103-02 Rev.D is designed as a 2.5V buffer DDR4C to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be DDR5T configured to support four unbuffered DDR DIMMS. DDR5C The PLL103-02 Rev.D can be used in conjunction ...

Page 2

... Type O Feedback clock for chipset. I Reference input from chipset. I Power Down Control input. When low, it will tri-state all outputs. Not connected. O These outputs provide True copies of BUF_IN. O These outputs provide complementary copies of BUF_IN. P 2.5V power supply. P Ground. PLL103-02 Rev.D Description Rev 01/11/01 Page 2 ...

Page 3

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Default Description 1 Reserved 0 Reserved 0 Enhanced DDR Drive Enhanced 25% 0 Reserved 1 DDR11T, DDR11C 1 DDR10T, DDR10C 1 DDR9T, DDR9C 1 DDR8T, DDR8C PLL103-02 Rev R Rev 01/11/01 Page 3 ...

Page 4

... Bit 2 10, 11 Bit Bit 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Default Description 1 DDR7T, DDR7C 1 DDR6T, DDR6C 1 DDR5T, DDR5C 1 DDR4T, DDR4C 1 DDR3T, DDR3C 1 DDR2T, DDR2C 1 DDR1T, DDR1C 1 DDR0T, DDR0C PLL103-02 Rev.D Rev 01/11/01 Page 4 ...

Page 5

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 SYMBOL SYMBOL V CONDITIONS All Inputs except I2C All inputs except I2C IOL = -12mA, VDD = 2.375V IOL = 12mA, VDD = 2.375V VDD = 2.375V, VOUT=1V VDD = 2.375V, VOUT=1.2V PLL103-02 Rev.D MIN. MAX 0 ...

Page 6

... SKEW pin ) Stabilization Time T ST Note: TBM measured 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 CONDITIONS Measured @ 1.5V Measured @ 0.4V ~ 2.4V Measured @ 2.4V ~ 0.4V All outputs equally loaded PLL103-02 Rev.D MIN. TYP. MAX. TBM (VDD/2) (VDD/2)+ VDD/2 -0.1 0.1 1.1 VDD-0 ...

Page 7

... MIN (0.20 - 0.41) 48PIN SSOP 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL103- PLL103-02 Rev.D 0.025 0.835 0.088 - 0.096 (2.250 - 2.450) 0.097 - 0.104 (2.467 - 2.642) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE ...

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