DS96-L147-203 CONEXANT [Conexant Systems, Inc], DS96-L147-203 Datasheet - Page 85

• Manufacturer Part Number: DS96-L147-203
• Description: SmartV.XX Modem
• Manufacturer: CONEXANT [Conexant Systems, Inc]

5.2.3
Table 5-2. Interrupt Sources and Reset Control
102199B
Notes:
1.
Bit
3 1
0
0
0
1
0
0
FIFO Mode only.
Interrupt Identification Register
Bit 2
0
1
1
1
0
0
Bit 1
IIR - Interrupt Identifier Register (Addr = 2)
0
1
0
0
1
0
Bit 0
1
0
0
0
0
0
The Interrupt Identifier Register (IIR) identifies the existence and type of up to five
prioritized pending interrupts. Four priority levels are set to assist interrupt processing in
the host. The four levels, in order of decreasing priority, are: Highest: Receiver Line
Status, 2: Receiver Data Available or Receiver Character Timeout, 3: TX Buffer Empty,
and 4: Modem Status.
When the IIR is accessed, the modem freezes all interrupts and indicates the highest
priority interrupt pending to the host. Any change occurring in interrupt conditions are
not indicated until this access is complete.
Bits 7-6
Bits 5-4
Bits 3-1
Bit 0
These two bits copy FCR0.
Always 0.
These three bits identify the highest priority pending interrupt (Table 5-2). Bit 3 is
When this bit is a 0, an interrupt is pending; IIR bits 1-3 can be used to determine the
applicable only when FIFO mode is selected, otherwise bit 3 is a 0.
source of the interrupt. When this bit is a1, an interrupt is not pending.
Priority
Highest
Level
CX81801-7x/8x SmartV.XX Modem Data Sheet
—
2
2
3
4
FIFO Mode.
Not Used.
Highest Priority Pending Interrupt.
Interrupt Pending.
None
Receiver Line
Status
Received Data
Available
Character Time-out
Indication
TX Buffer Empty
Modem Status
Interrupt Type
1
Conexant
None
Overrun Error OE (LSR1),
Parity Error (PE) (LSR2),
Framing Error (FE) (LSR3),
or Break Interrupt (BI) (LSR4)
Received Data Available (LSR0) or
RX FIFO Trigger Level (FCR6-
FCR7) Reached
The RX FIFO contains at least 1
character and no characters have
been removed from or input to the
RX FIFO during the last 4 character
times.
TX Buffer Empty
Delta CTS (DCTS) (MSR0),
Delta DSR (DDSR) (MSR1),
Trailing Edge Ring Indicator (TERI)
(MSR3), or Delta DCD (DCD)
(MSR4)
Interrupt Set and Reset Functions
Interrupt Source
1
—
Reading the LSR
Reading the RX Buffer or the RX
FIFO drops below the Trigger
Level
Reading the RX Buffer
Reading the IIR or writing to the
TX Buffer
Reading the MSR
Interrupt Reset Control
5-5