DS96-L147-203 CONEXANT [Conexant Systems, Inc], DS96-L147-203 Datasheet - Page 71

• Manufacturer Part Number: DS96-L147-203
• Description: SmartV.XX Modem
• Manufacturer: CONEXANT [Conexant Systems, Inc]

3.4.2.2
Table 3-21. Timing - Parallel Host Bus
102199B
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
1.
2.
3.
4.
5.
AS
AH
CS
CH
RD
DD
DRH
AS
AH
CS
CH
WT
DS
DWH
Symbol
When the host executes consecutive Rx FIFO reads, a minimum delay of 2 times the internal CPU clock cycle
plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of HRD# to the falling edge of the next Host
Rx FIFO HRD# clock.
When the Host executes consecutive Tx FIFO writes, a minimum delay of 2 times the internal CPU clock cycle
plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of HWT# to the falling edge of the next Host
Tx FIFO HWT# clock.
t
t
Clock frequency = 28.224 MHz clock.
DS
DWH
is measured from the point at which both HCS# and HWT# are active.
is measured from the point at which either HCS# and HWT# become inactive.
Address Setup
Address Hold
Chip Select Setup
Chip Select Hold
HRD# Strobe Width
Read Data Delay
Read Data Hold
Address Setup
Address Hold
Chip Select Setup
Chip Select Hold
HWT# Strobe Width
Write Data Setup (see Note 4)
Write Data Hold (see Note 5)
Parallel Host Bus Timing
The parallel host bus timing is listed in Table 3-21 and illustrated in Figure 3-10.
CX81801-7x/8x SmartV.XX Modem Data Sheet
Parameter
WRITE (See Notes 1, 2, 3, 4, and 5)
READ (See Notes 1, 2, 3, 4, and 5)
Conexant
Min
10
10
45
15
10
75
5
0
–
5
5
0
–
5
Max
25
20
–
–
–
–
–
–
–
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-39