sii3114 Silicon image, sii3114 Datasheet - Page 66

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

SiI3114 PCI to Serial ATA Controller
Data Sheet
System Software Data Register
Address Offset: 4C
Access Type: Read/Write
Reset Value: Undefined
This register is used by the software for non-resettable data storage. The contents are unknown on power-up and
are never cleared by any type of reset.
Flash Memory Address – Command + Status
Address Offset: 50
Access Type: Read/Write
Reset Value: 0x0800_0000
This register defines the address and command/status register for flash memory interface in the SiI3114. The
register bits are defined below.
SiI-DS-0103-D
• Bit [24] : Chnl2 Int Block (R/W) – Channel 2 Interrupt Block. This bit is set to block interrupts from Channel
• Bit [23] : Chnl1 Int Block (R/W) – Channel 1 Interrupt Block. This bit is set to block interrupts from Channel
• Bit [22] : Chnl0 Int Block (R/W) – Channel 0 Interrupt Block. This bit is set to block interrupts from Channel
• Bit [21:17] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [16] : M66EN (R) – PCI 66MHz Enable. This bit reflects input pin M66EN.
• Bit [15:12] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [11] : Chnl2 Module Rst (R/W) – Channel 2 Module Reset. This bit is set to reset the interface logic for
• Bit [10] : Chnl3 Module Rst (R/W) – Channel 3 Module Reset. This bit is set to reset the interface logic for
• Bit [09] : FF2 Module Rst (R/W) – FF2 Module Reset. This bit is set to reset the FIFO logic in Channel 2.
• Bit [08] : FF3 Module Rst (R/W) – FF3 Module Reset. This bit is set to reset the FIFO logic in Channel 3.
• Bit [07] : Chnl0 Module Rst (R/W) – Channel 0 Module Reset. This bit is set to reset the interface logic for
• Bit [06] : Chnl1 Module Rst (R/W) – Channel 1 Module Reset. This bit is set to reset the interface logic for
• Bit [05] : FF0 Module Rst (R/W) – FF0 Module Reset. This bit is set to reset the FIFO logic in Channel 0.
• Bit [04] : FF1 Module Rst (R/W) – FF1 Module Reset. This bit is set to reset the FIFO logic in Channel 1.
• Bit [03:02] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [01] : ARB Module Rst (R/W) – ARB Module Reset. This bit is set to reset the internal logic for the
• Bit [00] : PBM Module Rst (R/W) – PBM Module Reset. This bit is set to reset the internal logic for the PCI
2.
1.
0.
Channel 2.
Channel 3.
Channel 0.
Channel 1.
Arbiter.
Bus Master state machine.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
H
H
/ 24C
H
Reserved
System Software Data
58
Memory Address
© 2007 Silicon Image, Inc.
Silicon Image, Inc.