ch7301c Chrontel, ch7301c Datasheet - Page 7

• Manufacturer Part Number: ch7301c
• Description: Ch7301 Dvi Transmitter
• Manufacturer: Chrontel

CHRONTEL
3. I
Two distinct methods of transferring data to the CH7301C are described. They are:
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7301C is latched with both edges of the clock
(also referred to as dual-edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate, the data applied to
the CH7301C is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the
pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is
programmable. In dual edge transfer modes, the clock edge used to latch the first half of each pixel is programmable.
3.1 Interface Voltage Levels
The graphics controller interface can operate at a variable voltage level controlled by the voltage on the DVDDV pin. This
should be set to the maximum voltage of the interface (typically 3.3V or adjustable between 1.1 and 1.8V). The VREF
pin is the voltage reference for the data, date enable, clock and sync inputs and must be tied to DVDDV/2. This is typi-
cally done using a resistor divider.
3.2 Input Clock and Data Timing Diagram
The figure below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform represents the
input clock for the multiplexed data, clock at 2X pixel rate method. The second XCLK/XCLK* waveform represents the
input clock for the multiplexed data, clock at 1X pixel rate method.
201-0000-056
Table 3. Interface Timing
1
Symbol
V
V
t1
t2
DVDDV
D[11:0], H, V DE times measured when input equals Vref+100mV on rising edges, Vref-100mV on falling edges.
•
•
XCLK/
XCLK*
XCLK/
XCLK*
D[11:0]
DE
H
V
OH
OL
1
1
NPUT
Multiplexed data, clock input at 1X pixel rate
Multiplexed data, clock input at 2X pixel rate
Output high level of interface signals
Output Low level of interface signals
D[11:0] & DE to XCLK = XCLK* Delay (setup time)
XCLK = XCLK* to D[11:0] & DE Delay (hold time)
Digital I/O Supply Voltage
I
NTERFACE
V
V
V
Rev. 1.32,
V
V
V
V
V
V
V
V
V
OH
OH
OH
OL
OL
OL
OH
OL
OH
OL
OH
OL
5/24/2005
Parameter
t1
Figure 3. Interface Timing
1 VGA Line
64 P-OUT
t2
DVDDV -
1.1 – 5%
Min
-0.2
0.2
0.5
0.5
Typical
t1
t2
DVDDV +
3.3 + 5%
Max
0.2
0.2
CH7301C
Unit
ns
ns
V
V
V
7