ch7301c Chrontel, ch7301c Datasheet - Page 17

• Manufacturer Part Number: ch7301c
• Description: Ch7301 Dvi Transmitter
• Manufacturer: Chrontel

CHRONTEL
detect pin. The status bits, DACT[2:0] correspond to the termination of the three DAC outputs. However, the values
contained in these STATUS BITS ARE NOT VALID until a sensing procedure is performed. Use of this register
requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The
detection sequence works as follows:
1) Set the power management register (Register 49h) to enable all DAC’s, and set register 21h[0] = ’0’.
2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s.
3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and the
reference value. During this step, each of the three status bits corresponding to individual DAC outputs will be set if they
are CONNECTED.
4) Read the status bits. The status bits, DACT[2:0] now contain valid information which can be read to determine which
outputs are connected to a display monitor. Again, a “1” indicates a valid connection, a “0” indicates an unconnected
output.
Bit 5 of register CD can be read at any time to determine the level of the hot plug detection pin (HPDET). When the
HPDET is low, the DVI output driver will be shut down. When the hot plug detect pin changes state, and the DVI
output is selected, the HPINT output pin will be pulled low signifying a change in the DVI termination. At this
point, the HPIR bit in register 1Eh should be set high, then low to reset the hot plug detect circuit.
Bit 7 of register CD enables the hot plug interrupt detection signal output from the GPIO[1]/HPINT pin. A value of
‘1’ allows the hot plug detect circuit to pull the GPIO[1]/HPINT pin low when a change of state has taken place on
the hot plug detect pin (HPDET). A value of ‘0’ disables the interrupt signal. See also the description of the DVIT
bit.
DAC Control Register
Bit 0 of register DC selects the DAC bypass mode. If the input data format is digital RGB, a value of ‘1’ outputs the
incoming data directly at the DAC[2:0] outputs for the VGA-Bypass RGB output. If the input data format is digital
YCrCb, bit 0 of register 56h must be set to ’1’, together with bit 0 of register 21h set to ’1’, to output the analog
RGB from the DACs.
Bits 2-1 of register DC control the DAC gain. DACG1 should be low when the input data format is RGB (IDF = 0-
3), and high when the input data format is YCrCb (IDF = 4).
Bits 3 of register DC enables the HSYNC and VSYNC outputs.
201-0000-056
DEFAULT:
SYMBOL:
TYPE:
BIT:
Reserved Reserved Reserved Reserved SYNCO0
Rev. 1.32,
R/W
7
0
5/24/2005
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
DACG1
R/W
Symbol:
Address:
2
0
DACG0
R/W
CH7301C
1
0
DC
21h
DACBP
R/W
17
0
0