kac-9637 ETC-unknow, kac-9637 Datasheet - Page 26

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Register Set
The following section describes all available registers in the
KAC-9637 register bank and their function.
Register Name Device ID
Address
Mnemonic
Type
Reset Value
Register Name Silicon Revision
Address
Mnemonic
Type
Reset Value
Register Name Clock Generation Register
Address
Mnemonic
Type
Reset Value
Register Name Power Down/Reset Register
Address
Mnemonic
Type
Reset Value
www.kodak.com/go/imagers 585-722-4385
7:0
7:0
7
2:1
0
7:2
1
0
Bit
Bit
Bit
Bit
DevId
SiRev
HclkGen
SenReset
PwDn
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
00 Hex
DEVID
Read Only
47 Hex
01 Hex
REV
Read Only
Latest Silicon Hex
05 Hex
VCLKGEN
Read/Write
00 Hex.
06 Hex
PWD&RST
Read/Write
00 Hex.
Reserved.
Use to divide the frequency of
the sensors master clock input,
mclk, and generate the sen-
sor’s internal clock, hclk.
Reserved.
Reserved.
Set this self clearing bit to a
logic 1 to reset the sensor.
Set to a logic 1 to power down
the chip. All internal clocks will
be turned off in this mode.
Set to a logic 0, (the default) to
put the chip in power up mode.
Refer to section 8.2 for informa-
tion on the low power down
sequence.
00
01
10
11
The sensor’s device ID.
The sensor’s silicon revision.
÷1(default)
÷2
÷4
÷6
Description
Description
Description
Description
26
Register Name I
Address
Mnemonic
Type
Reset Value
Register Name Operation Control Register
Address
Mnemonic
Type
Reset Value
7:1
0
7:3
2
1
0
Bit
Bit
I2cDevAddr
AdvWr
MasterMode
RstzSoft
Bit Symbol
Bit Symbol
07 Hex
I2CMODE
Read/Write
AA Hex.
09 Hex
OPCTRL
Read/Write
02 Hex.
2
C Mode Register
Use to program the I
ible device address. By default,
the value is 55 hex.
Set to a logic 1 to activate the
I
advance
advance write mode, several
addresses can be written to
without the need to restart.
Set to a logic 0, the default, to
operate
interface
mode.
Reserved.
Set to a logic 1 to configure the
digital video port’s synchronisa-
tion’s signal to operate in master
mode.
Set to a logic 0 (the default) to
configure the digital video port’s
synchronisation signals to oper-
ate in slave mode.
This bit is reserved for factory
testing and must be set to a
logic 1 at all times.
Set this self clearing register to
a logic 1 to reset all state
machines contained in the inte-
grated smart timing and control
circuitry.
2
C compatible serial interface’s
Email:[e-mail]
Description
Description
the
in
write
I
standard
2
C
option.
2
compatible
C compat-
write
In