kac-9637 ETC-unknow, kac-9637 Datasheet - Page 16

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description (continued)
6.3
The KAC-9637 contains a clock generation module (figure 19)
that will create three clocks as follows:
www.kodak.com/go/imagers 585-722-4385
Hclk,
pclk
15
10
5
0
Clock Generation
0
the horizontal clock. This is an internal system
clock and can be programmed to be the input
clock (mclk) or mclk divided by 2,4 or 6. All
exposure times are in multiples of this clock.
To set the frequency of this clock the HclkGen
bits in the VCLKGEN register should be pro-
gramed.
the pixel clock. This is the external pixel clock
that appears at the digital video port. By default
pclk is free running and it’s frequency is always
equal to Hclk (see figure 19).
pclk can be programmed to the following
modes:
• Data Ready Mode, where pclk clock will go
• Reverse Polarity Mode, where the polarity of
active every time a valid pixel appears on the
data out bus by setting the PixClkMode bit of
the DVBUSCONFIG1 to a logic 1.
pclk is negated by programming the PixClk-
Pol bit in the DVBUSCONFIG2 register.
16
32
48
Figure 18. Gain Plot
PGA Gain Code
16
64
mclk
Figure 19. Clock Generation Module
80
PixClkMode
PixClkPol
data ready mode
÷
96
HclkGen
Email:[e-mail]
mux
112
Max. Gain = 16.0 dB
pclk
Hclk
128