kac-9630 ETC-unknow, kac-9630 Datasheet - Page 15

• Manufacturer Part Number: kac-9630
• Description: Cmos Image Sensor 126 H X 98 V Ultra Sensitive Global Shutter 580 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
MEMORY MAP
Register Set
The following section describes all available registers in the
KAC-9630 register bank and their function.
Register Name Silicon Rev & Bank Enable Register
Mnemonic
Address
Type
www.kodak.com/go/imagers 585-722-4385
7
6:3
4:0
Bit
OffsetBnkEn
SiRev
Bit Symbol
REV
00 Hex
Read/Write.
00h
01h
02h
03h
04h
05h
06h
07h
08h
ADDR
Assert to switch on the offset
adjustment bank. Note that the Off-
setDacEn bit must also be enabled.
This bit also enables the user to
access the POWSET register.
(Default setting is logic 0)
Reserved
Read only bits
The silicon revision register.
REV
MCFG
VGAIN
ITIMEL
IDLE
ITIMEH
POWSET
OFFSET
Register
Description
00h
00h
00h
0Ah
00h
00h
00h
Reset Value
15
Silicon Revision & Bank Enable Register
Main Configuration Register.
Video Gain Register
Integration Time Low Register
Idle Time Register
Integration Time High Register
Power Setting Register
Reserved
Offset Adjustment Register
Main Configuration
Register Name Main Configuration 0
Address
Mnemonic
Type:
Reset Value
7
6
5
4
3
2
1
0
Bit
DVBmode
PwrDown
PwdAmp
ByPassAmp
Res
TriDVP
Mode
Bit Symbol
Description
01 Hex
MCFG
Read/Write
01 Hex
Reserved
Assert to configure the digital image
data port to operate in serial mode.
Clear (the default) to configure the dig-
ital image data port to operate in paral-
lel mode.
Note: When this bit is set, pins d[2:7]
are tri-stated.
Assert to power down the sensor.
Clear (the default) this bit to power up
the sensor.
Assert to power down the programma-
ble video gain amplifier. Clear (the
default) to power up the video gain
amplifier.
Assert to route the analog video signal
from the output of the pixel core to the
input of the 8 bit A/D. Clear (the
default) to route the signal to the video
gain amplifier.
Assert to activate a system reset. The
integrated timing and control circuit
will automatically clear this bit.
(Default setting is logic 0).
Assert to tristate the digital video port,
clear (the default) enable sdo.
Asset (the default) to operate the sen-
sor in snapshot mode, clear to operate
the sensor in video mode.
Email:[e-mail]
Description