kac-9630 ETC-unknow, kac-9630 Datasheet - Page 13

• Manufacturer Part Number: kac-9630
• Description: Cmos Image Sensor 126 H X 98 V Ultra Sensitive Global Shutter 580 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Parallel Digital Image Data Port
By default the captured image is placed onto an 10-bit digital
image data port as shown in figure 19. The digital image data
port consists of an 8-bit digital data out bus (d[7:0]) and two syn-
chronisation signals (hsync & vsync).
The following sections provide a detailed description of the tim-
ing of the digital image data port.
Digital Image Data Out Bus (d[7:0])
Pixel data is output on an 8-bit digital video bus and is synchro-
nized to the positive edge of mclk.
Synchronisation Signals
Two synchronisation outputs are provided:
Horizontal Synchronisation Output Pin (hsync)
The horizontal synchronisation output pin, hsync, is used as an
indicator for row data.
The hsync output pin will go high at the start of each row and
remain at that level until the last pixel of that row is read out on
d[7:0] as shown in figure 20.
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mclk
vsync
hsync
d[7:0]
mclk
vsync
hsync
d[7:0]
hsync
vsync
8 Bit A/D
is the horizontal synchronisation output signal.
is the vertical synchronisation output signal in
video mode and the external frame trigger input
in snapshot mode.
Figure 19: Digital Video Port
C0
C0
row 100
row 100
Figure 23: Parallel Digital Image Data Port Timing Diagram in Snapshot Mode
C127
C127
Figure 22: Parallel Digital Image Data Port Timing Diagram In Video Mode
Image Data
Digital
horizontal
horizontal
Port
blanking
blanking
C0
C0
row 101
end of frame n
row 101
end of frame n
d[7:0]
hsync
vsync
C127
C127
Idle + Integration
start of frame n+1
Idle Time
13
Time
The hsync signal is synchronized to the positive edge of mclk.
Vertical Synchronisation Pin in Video Mode (vsync)
The vertical synchronisation pin, vsync, in video mode is an out-
put and is used as an indicator for pixel data within a frame.
The vsync pin will go high at the start of each frame and remain
at that level until the last pixel of that row in the frame is placed
on d[7:0] as shown in figure 21.
The vsync signal is synchronized to the positive edge of mclk.
Vertical Synchronisation Pin in Snapshot Mode (vsync)
The vertical synchronisation pin, vsync, in snapshot mode is an
input and is used as an external trigger to start the capture of a
single frame.
The vsync pin must be forced high for at least two “mclk” cycles
during the idle state of the sensor to trigger a single frame as
shown in figure 23.
The sensor can only be externally triggered when it is in the idle
state.
invalid pixel data
invalid pixel data
Integration
start of frame n+1
horizontal
Time
blanking
Figure 21: vsync Timing in Video Mode.
mclk
d[11:0]
mclk
d[11:0]
hsync
vsync
horizontal
blanking
C0
(Black Pixels)
Figure 20: hsync Timing
Row n
Frame n
row 1
(Black Pixels)
C0
C127
row 1
C127
horizontal
blanking
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horizontal
blanking
C0
Row n+1
Frame n+1
row 2
C0
row 2