ch7007a Chrontel, ch7007a Datasheet - Page 36

• Manufacturer Part Number: ch7007a
• Description: Ch7007a Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
Register 1CH, bit 4 controls whether the Data Start pin or the Horizontal Sync pin is used to determine the
start of active video. When this bit is low, the pin continues to operate as the BCO pin described in the
BCO register section. When this bit is high the pin becomes an input for the Data Start signal. A value of
0 is recommended if H syn is used as a reference to active video and the DSM bit5 also need to be set to
0.
Register 1CH, bit 5 determines how the Data Start input is used. A value of 0 is recommended, if DSEN
bit4 is set to 0.
Register 1CH, bits 7and 6 control the GPIO pins direction. When a GOENB bit is low, the corresponding
GPIO pin is an output pin. When a GOENB bit is high, the corresponding GPIO pin can be read to deter-
mine the level forced into it.
PLL Control Register
The following PLL and memory controls are available through the PLL control register:
MEM5V
PLL5VA
PLL5VD
PLLS
PLLCAP
PLLCPI
36
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
7
GOENB1
R/W
1
7
MEM5V should be set to 0 when DVDD is 3.3 volts, and 1 when DVDD is 5 volts.
PLL5VA is set to 1 when AVDD is 5 volts.
PLL5VD is set to 1 when DVDD is 5 volts. A value of 0 is used when DVDD is 3.3 volts (default).
When the PLL5VA is 1 PLLS should be 1. When PLL5VA is 0 PLLS should be 0.
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs
Mode is shown below.
The default value should be used.
6
GOENB0
R/W
1
6
5
DSM
R/W
1
5
PLLCPI
R/W
0
4
DSEN
R/W
1
4
PLLCAP
R/W
0
3
FSCI15
R/W
0
3
PLLS
R/W
1
201-0000-002
2
FSCI14
0
2
PLL5VD
0
R/W
R/W
Symbol:
Address: 1CH
Bits: 6
Symbol: PLLC
Address: 20H
Bits: 6
1
FSCI13
R/W
0
1
PLL5VA
R/W
1
Rev. 2.95, 6/24/2004
CH7007A
0
FSCI12
R/W
0
0
MEM5V
R/W
0