ch7007a Chrontel, ch7007a Datasheet - Page 26

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ch7007a

Manufacturer Part Number
ch7007a
Description
Ch7007a Digital Pc To Tv Encoder
Manufacturer
Chrontel
Datasheet

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Input Data Format Register
This register sets the variables required to define the incoming pixel data stream.
Reserved (bit 5): This bit should be set to 0.
DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71
µ
which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
The setting of the clock mode bits determines the clocking mechanism used in the CH7007. The clock modes are
shown in the table below. PCM controls the frequency of the P-OUT clock, and XCM identifies the frequency of the
XCLK input clock.
Note: Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format, there are
only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed at the
input of the device. Refer to the “Input Data Format Register” for these combinations.
Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK.
26
Table 17. Input Data Format
A, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
IDF[3:0]
7
CFRB
R/W
0
7
Not available
Not available
Not available
Not available
12-bit multiplexed RGB (24-bit color) input (“C” multiplex scheme)
12-bit multiplexed RGB (24-bit color) input (“I” multiplex scheme)
Not available
8-bit multiplexed RGB (16-bit color, 565) input
8-bit multiplexed RGB (15-bit color, 555) input
8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
6
M/S*
R/W
0
6
DACG
R/W
0
5
Reserved
5
Reserved
R/W
0
R/W
0
4
MCP
R/W
1
4
Description
3
IDF3
R/W
0
3
XCM1
R/W
0
201-0000-002
2
IDF2
R/W
0
2
XCM0
R/W
0
Address: 04H
Bits: 6
Address: 06H
Bits: 8
Symbol: IDF
Symbol: CM
1
IDF1
R/W
0
1
PCM1
R/W
0
Rev. 2.95, 6/24/2004
CH7007A
0
IDF0
R/W
0
0
PCM0
R/W
0
µ
A,

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