ch7007a Chrontel, ch7007a Datasheet - Page 32

• Manufacturer Part Number: ch7007a
• Description: Ch7007a Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
PLL M Value Register
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7007 is operating in master mode. In slave mode, an external pixel clock is
used instead of the frequency reference, and the division factor is determined by the XCM[1:0] value. This register
contains the lower 8 bits of the complete 9-bit M value.
PLL N Value Register
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL
phase detector, when the CH7007 is operating in master mode. In slave mode, the value of ‘N’ is always 1. This
register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master mode and is
calculated according to the equation below:
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below.
32
Table 21. M and N Values for Each Mode
Mode
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
10
11
12
13
0
1
2
3
4
5
6
7
8
9
512x384, PAL, 5:4
512x384, PAL, 1:1
512X384, NTSC, 5:4
512X384, NTSC, 1:1
720X400, PAL, 5:4
720X400, PAL, 1:1
720X400, NTSC, 5:4
720X400, NTSC, 1:1
640X400, PAL, 5:4
640X400, PAL, 1:1
640X400, NTSC, 5:4
640x400, NTSC, 1:1
640X400, NTSC, 7:8
640X480, PAL, 5:4
Standard, Scaling Ratio
VGA Resolution, TV
7
M7
R/W
0
7
N7
R/W
1
6
M6
R/W
1
6
N6
R/W
0
N 10-
bits
126
339
106
108
190
5
M5
R/W
0
5
N5
R/W
0
110
20
53
70
94
22
20
9
9
Fpixel = Fref* [(N+2) / (M+2)]
M 9-
bits
138
13
89
63
26
63
33
61
63
11
89
13
4
3
4
M4
R/W
0
4
N4
R/W
0
Mode
14
15
16
17
18
19
20
21
22
23
24
25
26
3
M3
R/W
0
3
N3
R/W
0
640x480, PAL, 1:1
640X480, PAL, 5:6
640X480, NTSC, 1:1
640X480, NTSC, 7:8
640X480, NTSC, 5:6
800X600, PAL, 1:1
800X600, PAL, 5:6
800X600, PAL, 3:4
800X600, NTSC, 5:6
800X600, NTSC, 3:4
800X600, NTSC, 7:10
720X576, PAL, 1:1
720X480, NTSC, 1:1
Standard, Scaling Ratio
VGA Resolution, TV
201-0000-002
2
M2
0
2
N2
0
R/W
R/W
Address: 14H
Bits: 8
Symbol: PLLN
Address: 15H
Bits: 8
Symbol: PLLM
1
M1
R/W
0
1
N1
R/W
0
Rev. 2.95, 6/24/2004
N 10-
CH7007A
bits
126
190
647
284
302
110
86
94
62
31
31
9
9
0
M0
R/W
1
0
N0
R/W
0
M 9-
bits
313
103
63
63
89
33
33
19
89
33
33
4
3