ch7007a Chrontel, ch7007a Datasheet - Page 29

• Manufacturer Part Number: ch7007a
• Description: Ch7007a Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
Sync Polarity Register
This register provides selection of the synchronization signal input to, or output from, the CH7007.
Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical
sync will use a fixed pulse width of 1 line.
Power Management Register
This register provides control of the power management functions, a software reset (Reset*) and the SCART output
enable. The CH7007 provides programmable control of its operating states, as described in the table below.
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself
and the serial port state machines.
SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7007 will operate normally, outputting Y/C
and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from
the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description
sections.
201-0000-002
Table 19. Power Management
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
000
001
010
011
1XX
• HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low and a
• VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low and a value of
• SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7007. A
• DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from
PD[2:0]
value of one means the horizontal sync is active high.
one means the vertical sync is active high.
value of one means that H and V sync are output from the CH7007.
the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes
on the pixel input stream. Note that this will only be valid for the YCrCb input modes.
7
7
Rev. 2.95, 6/24/2004
Composite Off
Power Down
S-Video Off
Normal (On)
Full Power Down
Operating State
6
6
5
5
CVBS DAC is powered down.
Most pins and circuitry are disabled (except for the buffered clock outputs
which are limited to the 14MHz output and VCO divided outputs).
S-Video DACs are powered down.
All circuits and pins are active.
All circuitry is powered down except serial port interface circuit.
4
4
SCART
R/W
0
3
DES
R/W
0
3
Reset*
R/W
1
Functional Description
2
SYO
R/W
0
2
PD2
R/W
1
Symbol: SPR
Address: 0DH
Bits: 4
Symbol: PMR
Address: 0EH
Bits: 5
1
VSP
R/W
0
1
PD1
R/W
0
CH7007A
0
HSP
R/W
0
0
PD0
R/W
1
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