ax88783lf ASIX Electronics Corporation, ax88783lf Datasheet - Page 26

• Manufacturer Part Number: ax88783lf
• Description: 2-port 10/100m Fast Ethernet Controller
• Manufacturer: ASIX Electronics Corporation

MII1_REFCLK
MII1_TX_EN
MII1_TXD0
MII1_TXD1
MII1_REFCLKO
MII1_CRSDV
MII1_RXD0
MII1_RXD1
MII1_MDIO
MII1_MDC
MII1_CRS
MII1_COL
AX88783
Signal Name
Pin #
31
33
32
34
35
36
37
38
43
44
49
48
47
46
29
30
2.2.5 Reverse RMII Mode
2.2.6 Port 1 Multi-Function Pin Summary
MII1_RX_CLK
MII1_RX_COL
MII1_RX_CRS
MII1_RX_DV
MII1_RXD0
MII1_RXD1
MII1_RXD2
MII1_RXD3
MII1_TX_CLK
MII1_TX_EN
MII1_TXD0
MII1_TXD1
MII1_TXD2
MII1_TXD3
MII1_MDIO
MII1_MDC
MII Mode
B3/8mA/T
O3/8mA
O3/8mA
O3/8mA
O3/8mA
I/O
I3
I3
I3
I3
I3
I3
I3
MII1_TX_CLK
Pull-Down
MII1_CRS
MII1_TX_EN
MII1_TXD0
MII1_TXD1
MII1_TXD2
MII1_TXD3
MII1_RX_CLK
MII1_RX_DV
MII1_RXD0
MII1_RXD1
MII1_RXD2
MII1_RXD3
MII1_MDIO
MII1_MDC
AX88783
Reverse MII Mode
Pin No.
31
34
35
36
43
44
49
48
29
30
32
33
Port 1 50MHz RMII reference clock input ± 50 PPM with a duty cycle
between 35% and 65% inclusive.
Port 1 Transmit data valid synchronously with respect to the rising edge
of MII1_REFCLK. MII1_TX_EN is asserted high when valid data is
present on transmit data bus [1:0].
Port 1 Transmit data bit 0 synchronously with respect to the rising edge
of MII1_REFCLK.
Port 1 Transmit data bit 1 synchronously with respect to the rising edge
of MII1_REFCLK.
Port 1 50MHz reference clock output if ICR [13] is set to one.
Port 1 Receive data enable synchronously with respect to the rising
edge of MII1_REFCLK. MII1_CRSDV is asserted high to indicate a
valid receive data bus [1:0]
Port 1 Receive data bit 0 synchronously with respect to the rising edge
of MII1_REFCLK.
Port 1 Receive data bit 1 synchronously with respect to the rising edge
of MII1_REFCLK.
MII management data. Serial data input/output transferred from/to the
externally connected MAC device. The transfer protocol should
conform to the IEEE 802.3u MII spec.
MII management clock input from the externally connected Ethernet
MAC device. All data transferred on MDIO are synchronized to the
rising edge of this clock.
Note: P1SMR0 Slave MDIO Register need to be programmed
Pull-Down with a 4.7K ohm resistor to ground
Pull-Down with a 4.7K ohm resistor to ground
MII1_REFCLK
Pull-Down
Pull-Down
MII1_CRSDV
MII1_RXD0
MII1_RXD1
NC
NC
MII1_REFCLKO
MII1_TX_EN
MII1_TXD0
MII1_TXD1
NC
NC
MII1_MDIO
MII1_MDC
26
RMII Mode
2-Port 10/100M Fast Ethernet Controller
Description
ASIX ELECTRONICS CORPORATION
MII1_REFCLK
Pull-Down
Pull-Down
MII1_TX_EN
MII1_TXD0
MII1_TXD1
NC
NC
MII1_REFCLKO
MII1_CRSDV
MII1_RXD0
MII1_RXD1
NC
NC
MII1_MDIO
MII1_MDC
Reverse RMII Mode PHY Mode
Non-PCI 8/16/32-Bit
AX88782/AX88783
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P1_LED0
P1_LED1
P1_LED2
NC
NC
NC