ax88783lf ASIX Electronics Corporation, ax88783lf Datasheet - Page 24

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ax88783lf

Manufacturer Part Number
ax88783lf
Description
2-port 10/100m Fast Ethernet Controller
Manufacturer
ASIX Electronics Corporation
Datasheet

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Part Number
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Quantity
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Part Number:
AX88783LF
Manufacturer:
TEXAS
Quantity:
125
MII1_TX_CLK
MII1_CRS
MII1_COL
MII1_TX_EN
MII1_TXD0
MII1_TXD1
MII1_TXD2
MII1_TXD3
MII1_RX_CLK
MII1_RX_DV
MII1_RXD0
MII1_RXD1
MII1_RXD2
MII1_RXD3
MII1_MDIO
MII1_MDC
Signal Name
2.2.3 Reverse MII Mode
B3/8mA/T
O3/8mA
O3/8mA
O3/8mA
O3/8mA
O3/8mA
O3/8mA
O3/8mA
I/O
I3
I3
I3
I3
I3
I3
I3
I3
AX88783
Pin No.
31
32
33
34
35
36
37
38
44
49
48
47
46
29
30
43
Port 1 Carrier Sense. Please connect this signal to MII1_TX_EN
Port 1 Transmit data bit 0 synchronously with respect to the rising
Port 1 Transmit data bit 1 synchronously with respect to the rising
Port 1 Transmit data bit 2 synchronously with respect to the rising
Port 1 Transmit data bit 3 synchronously with respect to the rising
MII management clock input from the externally connected Ethernet
Port 1 Transmit clock output
enable signal.
Pull-Down with a 4.7KOhm resistor to ground. Reverse MII mode
only support full duplex.
Port 1 Transmit data valid. MII1_TX_EN is asserted high when valid
data is present on transmit data bus [3:0].
edge of MII1_TX_CLK.
edge of MII1_TX_CLK.
edge of MII1_TX_CLK.
edge of MII1_TX_CLK.
Port 1 Receive clock output
Port 1 Receive data enable. MII1_RX_DV is asserted high to indicate
a valid receive data bus [3:0]
Port 1 Receive data bit 0 synchronously with respect to the rising
edge of MII1_RX_CLK.
Port 1 Receive data bit 1 synchronously with respect to the rising
edge of MII1_RX_CLK.
Port 1 Receive data bit 2 synchronously with respect to the rising
edge of MII1_RX_CLK.
Port 1 Receive data bit 3 synchronously with respect to the rising
edge of MII1_RX_CLK.
MII management data. Serial data input/output transferred from/to
the externally connected MAC device. The transfer protocol should
conform to the IEEE 802.3u MII spec.
MAC device. All data transferred on MDIO are synchronized to the
rising edge of this clock.
Note: P1SMR0 Slave MDIO Register need to be programmed
24
2-Port 10/100M Fast Ethernet Controller
ASIX ELECTRONICS CORPORATION
Description
Non-PCI 8/16/32-Bit
AX88782/AX88783

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