sii1162 Silicon image, sii1162 Datasheet - Page 17

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sii1162

Manufacturer Part Number
sii1162
Description
Panellink Transmitter
Manufacturer
Silicon image
Datasheet

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SiI 1162 PanelLink Transmitter
Data Sheet
I
I
Notes:
1.
2.
3.
4.
5.
SiI -DS-0081-B
2
2
Addr.
C Register Mapping
C Registers
0xA
0xB
0xC
0xD
0xE
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xF
All values are Bit 7(msb) and Bit 0(lsb).
Registers that can be written and read from are listed as (RW) while registers that can be read only are listed as (RO).
After the RESET signal is de-asserted in I
R/W registers do not retain their value after a reset, but are set back to the default values shown in the table.
Registers and bits listed as RSVD are reserved and for Silicon Image, Inc. use only.
Default setting for the VDJK register 0x0C is 0x89, which is optimum for most applications.
VLOW
RSVD
(RO)
Bit 7
RSVD
Bit 6
DK[1:0] (RW)
MSEL[2:0] (RW)
(R/W)
Bit 5
VEN
2
RSVD
C mode, only MDI retains the programmed value set before the reset. All other
(R/W)
FRQ_HIGH (RO)
HEN
Bit 4
FRQ_LOW (RO)
DEV_REV (RO)
VND_IDH (RO)
DEV_IDH (RO)
VND_IDL (RO)
DEV_IDL (RO)
VDJK[7:0]
RSVD
RSVD
RSVD
RSVD
RSVD
TSEL
(RW)
Bit 3
13
RSVD
RSEN
(RO)
Bit 2
CTL[3:0] (RW)
HTPLG
EDGE
(RW)
(RO)
Bit 1
(RW)
(RW)
Bit 0
PD#
MDI
Default
0x01
0x00
0x06
0x00
0x00
0x20
0x64
0x90
0x89
0x34
0x06
Notes
3
5

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