as28f128j3a Austin Semiconductor, Inc., as28f128j3a Datasheet - Page 5

• Manufacturer Part Number: as28f128j3a
• Description: Plastic Encapsulated Microcircuit 128mb, X8 And X16 Q-flash Memory Even Sectored, Single Bit Per Cell Architecture
• Manufacturer: Austin Semiconductor, Inc.

AS28F128J3A
Rev. 5.5 3/09
Key:
[IA]
[ID]
[BA]
[QA]
[PA]
[QD]
[SRD]
Notes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Memory Command Set Operations
READ ARRAY
READ IDENTIFIER CODES
READ QUERY
READ STATUS REGISTER
CLEAR STATUS REGISTER
WRITE TO BUFFER
WORD/BYTE PROGRAM
BLOCK ERASE
BLOCK ERASE/PROGRAM SUSPEND
BLOCK ERASE/PROGRAM RESUME
CONFIGURATION
SET BLOCK LOCK BITS
CLEAR BLOCK LOCK BITS
PROTECTION PROGRAM
Identifier Code address
Data read from identifier Code
Address within a Block
Query data base Address
Address of Memory location to be programmed
Data read from Query data base
Data read from Status Register
Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.
If the ISM is running, only DQ7 is valid; DQ15-DQ8 and DQ6-DQ0 are placed in High-Z
After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for WRITING
The number of Bytes/words to be written to the write buffer = n+1, where n=byte/word count argument. Count ranges on this device
mode are n=00H to n=1Fh and for word mode, n=0000h to 000Fh. The third and consecutive bus cycles, as determined by n, are for writing data
into the write buffer. The CONFIRM command (D0h) is expected after exactly n+1 WRITE cycles; any other command at that point in the
sequence aborts the WRITE-to-BUFFER operation.
The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued
Attempts to issue a BLOCK ERASE or PROGRAM to a locked block will fail
Etiher 40h or 10h is recognized by the ISM as the byte/word program setup
PROGRAM SUSPEND can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is inititated. The CLEAR BLOCK
LOCK BITS operation simultaneously clears all block lock bits.
Command
AUSTIN SEMICONDUCTOR, INC.
Scalable or Basic Command
Austin Semiconductor, Inc.
Set [SCS or BCS]
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS
SCS
SCS
SCS
Bus Cycles Operation
>/=2
>2
1
2
1
2
2
1
1
2
2
2
2
5
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
First Bus Cycle
Address
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
40h or 10h
Data
D0h
FFh
90h
98h
70h
50h
E8h
20h
B0h
B8h
60h
60h
C0h
Operation
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
AS28F128J3A
Second Bus Cycle
Address
QA
BA
PA
BA
BA
PA
IA
X
X
X
Q-Flash
PEM
PEM
PEM
PEM
PEM
Data
SRD
D0h
D0h
01h
QD
PD
PD
CC
ID
N
for byte
Notes
3,4,5
6,7
5,6
7,8
1
2
7