as28f128j3a Austin Semiconductor, Inc., as28f128j3a Datasheet

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as28f128j3a

Manufacturer Part Number
as28f128j3a
Description
Plastic Encapsulated Microcircuit 128mb, X8 And X16 Q-flash Memory Even Sectored, Single Bit Per Cell Architecture
Manufacturer
Austin Semiconductor, Inc.
Datasheet
AS28F128J3A
Rev. 5.5 3/09
Plastic Encapsulated Microcircuit
128Mb, x8 and x16 Q-FLASH Memory
Even Sectored, Single Bit per Cell Architecture
GENERAL DESCRIPTION
ASI’s, AS28F128J3A Enhanced or Mil-Temp variant of
Numonyx’s Q-Flash family of devices, is a nonvolatile,
electrically block-erasable (FLASH), programmable memory
device manufactured using Numonyx’s 0.15um process
technology. This device containing 134,217,728 bits organized
as either 16,777,218 (x8) or 8,388,608 bytes (x16). The device is
uniformly sectored with one hundred and twenty eight 128KB
ERASE blocks.
FEATURES
For in-depth functional product detail and Timing
Diagrams, please reference Numonyx’s full product
Datasheet:
EMBEDDED FLASH MEMORY (J3vD)
Dated: December 2007
100% Pin and Function compatible to Intel’s MLC
Family
NOR Cell Architecture
2.7V to 3.6V VCC
2.7V to 3.6V or 5V VPEN (Programming Voltage)
Asynchronous Page Mode Reads
Manufacturer’s ID Code:
Industry Standard Pin-Out
Fully compatible TTL Input and Outputs
Common Flash Interface [CFI]
Scalable Command Set
Automatic WRITE and ERASE Algorithms
5.6us per Byte effective programming time
128 bit protection register
Enhanced data protection feature with use of VPEN=VSS
Security OTP block feature
100,000 ERASE cycles per BLOCK
Automatic Suspend Options:
Available Operating Ranges:
Numonyx 0x89h
64-bit unique device identifier
64-bit user programmable OTP cells
Block ERASE SUSPEND-to-READ
Block ERASE SUSPEND-to-PROGRAM
PROGRAM SUSPEND-to-READ
Enhanced
Mil-Temperature [-XT]
AUSTIN SEMICONDUCTOR, INC.
[-ET]
Austin Semiconductor, Inc.
-40
-55
o
o
C to +105
C to +125
o
o
C
C
1
This device features in-system block locking. They also have
a Common FLASH Interface [CFI] that permits software
algorithms to be used for entire families of devices. The
software is device-independent, JEDEC ID-independent with
forward and backward compatibility.
CE1
CE0
A22
A21
A18
A17
A16
VCC
A13
A12
A10
A9
A7
A6
A5
A4
A1
A20
A19
A15
A14
VPEN
RP\
A11
A8
VSS
A3
A2
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A
B
C
D
E
F
G
H
BYTE\
DQ8
CE2
A23
1
A2
A3
A4
A1
DQ1
DNU
VSS
DQ0
A6
A5
A0
2
A7
PIN ASSIGNMENT
DQ10
DQ2
DQ9
VCC
A10
A11
A8
A9
3
64-Ball FBGA
VPEN
VCCQ
DQ11 DQ12
DQ3
CE0
VSS
A12
RP\
4
DQ13
DNU
DQ4
DQ5
A13
A14
A15
5
AS28F128J3A
DNU
DNU
DNU
VSS
VCC
DNU
DNU
DQ6
6
DQ15
DQ14
DNU
DQ7
A16
A18
A19
A20
7
DNU
STS
WE\
A22
CE1
A21
OE\
A17
8
Q-Flash
PEM
PEM
PEM
PEM
PEM
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
WE\
OE\
STS
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VCCQ
VSS
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE\
A23
CE2

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as28f128j3a Summary of contents

Page 1

... Datasheet: EMBEDDED FLASH MEMORY (J3vD) Dated: December 2007 GENERAL DESCRIPTION ASI’s, AS28F128J3A Enhanced or Mil-Temp variant of Numonyx’s Q-Flash family of devices nonvolatile, electrically block-erasable (FLASH), programmable memory device manufactured using Numonyx’s 0.15um process technology. This device containing 134,217,728 bits organized as either 16,777,218 (x8) or 8,388,608 bytes (x16) ...

Page 2

... LOCK BIT configuration. When HIGH, STS indicates that the ISM is ready for a new command. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 PEM PEM PEM PEM PEM AS28F128J3A Q-Flash Input Buffer 128KB Memory Block (0) 128KB Memory Block (1) 128KB Memory Block (2) 128KB Memory Block (3) WRITE ...

Page 3

... Separate/Isolated Voltage supply for Input/Output bus. Allows Supply 43 voltage matching to different interface standards. Supply 9, 37 Power Supply: 2.7V 3.6V Supply 21,42,48 Ground 1,30,56 No electrical connection or function Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 AS28F128J3A Q-Flash CE1 CE0 Device VIL VIL Enabled VIL VIH Disabled VIH VIL Disabled ...

Page 4

... VIH X VIL VIH X VIL VIH X Dout VIH VIL VPENH Din Test Conditions 4 AS28F128J3A Notes Address 1,2,3 X High Z (VOH with External PU High Z (VOH with External PU) 4 See Table 31 of Numonyx DS High Z (VOH with External PU) 5 See CFI Query of Numonyx DS High Z (VOH with External PU) ...

Page 5

... SCS/BCS 1 WRITE SCS/BCS 1 WRITE SCS 2 WRITE SCS 2 WRITE SCS 2 WRITE 2 WRITE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 AS28F128J3A First Bus Cycle Second Bus Cycle Address Data Operation Address X FFh X 90h READ IA X 98h READ QA X 70h ...

Page 6

... BYTE\ to Output in High Z CEx High to CEx Low Page Address Access Reset Specifications RP\ Pulse Low time RP\ High to RESET during BLOCK ERASE, PROGRAM, or Lock Bit configuration Notes to Switching Specifications: 1. Sampled, not 100% tested AS28F128J3A Rev. 5.5 3/09 AS28F128J3A Symbol 128Mb Min Max tRS 1.0 tCS 0 tWP 70 ...

Page 7

... AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. Mechanical Diagram TSOP, Type 1, 56 Pin (Dimensions in mm) 0.15 +0.03, -0.02 AS28F128J3A Rev. 5.5 3/09 20.00 +/- 0.25 18.40 +/- 0.08 1.20 MAX. SEE DETAIL A 0.25 Gage Plane 0.10 + 0.10, -0.05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 PEM PEM PEM PEM PEM AS28F128J3A Q-Flash 0.50 TYP. 0.20 +/- 0.05 0.25 0.10 DETAIL A 0.50 +/- 0.10 0.80 TYP. ...

Page 8

... Configuration o Enhanced Operating Range ( +105 AS28F128J3ARG 15/ET 128Mb, x8/x16 Q Flash AS28F128J3APBG 15/ET 128Mb, x8/x16 Q Flash 0 Extended Operating Range ( +125 AS28F128J3ARG 15/XT 128Mb, x8/x16 Q Flash AS28F128J3APBG 15/XT 128Mb, x8/x16 Q Flash AS28F128J3A Rev. 5.5 3/09 Ball A1 7.00 Ball A1 ID 1.00 Typ. 13.00 +/-0.10 6.50 +/-0.05 Solder Ball Material: 62% Sn., 36% Pb., 2% Ag. Speed (ns) Pkg. ...

Page 9

... Q-FLASH Memory Even Sectored, Single Bit per Cell Architecture REVISION HISTORY Rev # History 5.5 Updated with Numonyx Info AS28F128J3A Rev. 5.5 3/09 AS28F128J3A Release Date March 2009 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 PEM PEM PEM PEM ...

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