as28f128j3a Austin Semiconductor, Inc., as28f128j3a Datasheet - Page 2

• Manufacturer Part Number: as28f128j3a
• Description: Plastic Encapsulated Microcircuit 128mb, X8 And X16 Q-flash Memory Even Sectored, Single Bit Per Cell Architecture
• Manufacturer: Austin Semiconductor, Inc.

AS28F128J3A
Rev. 5.5 3/09
Additionally, the Scaleable Command Set [SCS] allows a single,
simple software driver in all host systems to work with all SCS
compliant FLASH memory devices. The SCS provides the
fastest system/device data transfer rates and minimizes the
device and system-level implementation costs.
To optimize the processor-memory interface, the device
accommodates VPEN, which is switchable during BLOCK
ERASE, PROGRAM, or LOCK BIT configurations and in
addition can be hard-wired to VCC all dependent on the end
application(s). VPEN is treated as an input pin to enable
ERASING, PROGRAMMING, and BLOCK LOCKING. When
VPEN is lower than the VCC lockout voltage (VLKO), all
program functions are disabled. BLOCK ERASE SUSPEND
mode enables the user to stop BLOCK ERASE to READ data
from or PROGRAM data to any other blocks. Similarly,
PROGRAM SUSPEND mode enables the user to SUSPEND
PROGRAMMING to READ data or execute code from any
un-suspended block(s).
Functional Block Diagram:
VPEN
WAIT
OE\
WP\
WE\
RP\
CLK
STS
CEx
CNTL
Logic
I/O
Command
Execution
AUSTIN SEMICONDUCTOR, INC.
Logic
[CEL]
(Current)
Austin Semiconductor, Inc.
Control
Buffer/
Power
ADDR
Latch
Register [BCR]
Configuration
Bus
Register
ISM
Status
Switch
Pump
VPP
Counter
ADDR.
Identification
2
Register
VPEN serves as an input with 2.7V, 3.3V or 5V levels for
application programming. VPEN in this Q-Flash device can
provide data protection when connected to ground. This pin
also enables PROGRAM or ERASE LOCKOUT functions/
controls during power transitions.
This device is an even-sectored device architecture offering
individual BLOCK LOCKING that can LOCK and UN-LOCK a
block using the SECTOR LOCK BITS command sequence.
Status [STS] is a logic signal output that gives an additional
indicator of the internal state machine [ISM] activity by
providing a hardware signal of both the status and status
masking. This status indicator minimizes central processing
unit overhead and system power consumption. In the default
mode, STS acts as an RY/BY\ pin. When LOW, STS indicates
that the ISM is performing a BLOCK ERASE, PROGRAM, or
LOCK BIT configuration. When HIGH, STS indicates that the
ISM is ready for a new command.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Decode
Control
Dec.
Erase
Block
Y
X
Query
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
128KB Memory Block (3)
128KB Memory Block (n)
WRITE/ERASE Bit
Sense Amplifiers
Compare and
Y - Select
Control
Verify
AS28F128J3A
WRITE
Buffer
Output
Buffer
Buffer
Input
Q-Flash
PEM
PEM
PEM
PEM
PEM
DQ0-8 or
DQ0-15