act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 7

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

memory system page mapping. It consists of an instruction
address translation buffer, or ITLB, a data address
translation buffer, or DTLB, a Joint TLB, or JTLB, and
coprocessor registers used by the virtual memory mapping
sub-system.
System Control Coprocessor Registers
coprocessor (CP0) registers internally. These registers
provide the path through which the virtual memory
system’s page mapping is examined and modified,
exceptions are handled, and operating modes are controlled
(kernel vs. user mode, interrupts enabled or disabled, cache
features). In addition, the ACT 7000ASC includes
registers to implement a real-time cycle counting facility,
to aid in cache and system diagnostics, and to assist in data
error detection.
interrupt handling capabilities of the ACT 7000ASC, both
the data and control register spaces of CP0 are supported by
the ACT 7000ASC. In the data register space, that is the
space accessed using the MFC0 and MTC0 instructions,
the ACT 7000ASC supports the same registers as found in
the RM5200, R4000 and R5000 families. In the control
space, that is the space accessed by the previously unused
CTC0 and CFC0 instructions, the ACT 7000ASC supports
five new registers. The first three of these new 32-bit
registers support the enhanced interrupt handling
capabilities and are the Interrupt Control, Interrupt Priority
The memory management unit controls the virtual
The ACT 7000ASC incorporates all system control
To support the non-blocking caches and enhanced
LLAddr
SCD7000A Rev B
17*
47
0
PageMask
TagLo
EntryHi
(entries protected
28*
10*
5*
from TLBWR)
Used for memory
management
TLB
EntryLo0
EntryLo1
TagHi
2*
3*
29*
Random
Figure 4 – CP0 Registers
* Registered number
Config
Wired
Index
PRid
Info
15*
16*
7*
0*
1*
6*
7
Context
Watch2
Status
Count
EPC
ECC
12*
14*
19*
26*
Level Lo (IPLLO), and Interrupt Priority Level Hi (IPLHI)
registers. These registers are described further in the
section on interrupt handling. The other two registers,
Imprecise Error 1 and Imprecise Error 2, have been added
to help diagnose bus errors which occur on non-blocking
memory references.
Virtual to Physical Address Mapping
addressing:
provide a secure environment for user processes. Bits in the
CP0 Status register determine which virtual addressing
mode is used. In the user mode, the ACT 7000ASC
provides a single, uniform virtual address space of 256GB
(2GB in 32-bit mode).
address spaces, totalling 1024GB (4GB in 32-bit mode),
are simultaneously available and are differentiated by the
high-order bits of the virtual address.
supervisor mode in which the virtual address space is
256.5GB (2.5GB in 32-bit mode), divided into three
regions based on the high-order bits of the virtual address.
Figure 5 shows the address space layout for 32-bit
operation.
4*
9*
Figure 4 shows the CP0 registers.
The ACT 7000ASC provides three modes of virtual
• user mode
• supervisor mode
• kernel mode
This mechanism is available to system software to
When operating in the kernel mode, four distinct virtual
The
Used for exception
ACT 7000ASC processor
processing
BadVAddr
ErrorEPC
CacheErr
Compare
Xcontext
Watch1
Cause
11*
13*
18*
20*
27*
30*
8*
Perf Counter
Perf Ctr Cntrl
Watch Mask
25*
22*
24*
Control Space Registers
Imp Error 1
Imp Error 2
IntControl
also
IPLLO
IPLHI
18*
19*
20*
26*
27*
supports
a