act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 6

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

dynamically determining the size of the input operands, the
ACT 7000ASC is able to maximize throughput while still
using an area efficient implementation.
Floating-Point Coprocessor
fully pipe-lined floating-point coprocessor which includes
a floating-point register file and autonomous execution
units for multiply/ add/convert and divide/square root. The
floating-point
co-execution unit, decoding and executing instructions in
parallel with, and in the case of floating-point loads and
stores, in cooperation with the M pipe of the integer unit.
As described earlier, the superscalar capabilities of the
ACT 7000ASC
instructions to issue concurrently with integer instructions.
Floating-Point Unit
supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is
broken into a separate divide/square root unit and a
pipelined multiply/add unit. Overlap of divide/square root
and multiply/add is supported.
floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely
important in object-oriented programming environments
and highly desirable for debugging in any environment.
floating-point add, subtract, multiply, multiply-add, divide,
square root, reciprocal, reciprocal square root, conditional
moves, conversion between fixed-point and floating-point
format, conversion between floating-point formats, and
floating-point compare. Table 5 gives the latencies of the
floating-point instructions in internal processor cycles.
Floating-Point General Register File
of thirty-two 64-bit registers. With the floating-point load
and store double instructions, LDC1 and SDC1, the
floating-point unit can take advantage of the 64-bit wide
data cache and issue a floating-point coprocessor load or
store double-word instruction in every cycle.
registers; one for determining configuration and revision
information for the coprocessor and one for control and
status information. These registers are primarily used for
diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
By pipelining the multiply-accumulate function and
The ACT 7000ASC incorporates a high-performance
The ACT 7000ASC floating-point execution unit
The
The floating-point unit’s operation set includes
The floating-point general register file, FGR, is made up
The floating-point control register file contains two
SCD7000A Rev B
ACT 7000ASC
coprocessor
allow
floating-point
maintains
is
a
tightly
fully
computation
coupled
precise
6
ports and two write ports, and is fully bypassed to minimize
operation latency in the pipeline. Three of the read ports
and one write port are used to support the combined
multiply-add instruction while the fourth read and second
write port allows a concurrent floating-point load or store
and conditional moves.
System Control Coprocessor (CP0)
architecture is responsible for the virtual memory
sub-system, the exception control system, and the
diagnostics capability of the processor. In the MIPS
architecture, the system control coprocessor (and thus the
kernel software) is implementation dependent. For memory
management, the ACT 7000ASC CP0 is logically identical
to that of the RM5200 Family and R5000. For interrupt
exceptions and diagnostics, the ACT 7000ASC is a
superset of the RM5200 Family and R5000 implementing
additional features described later in the sections on
Interrupts,
Performance Counter facility.
To support superscalar operations, the FGR has four read
The system control coprocessor (CP0) in the MIPS
fmov, fmovc
Operation
fabs, fneg
Table 5 – Floating Point Latencies and
fcvt.d.w
fcvt.s.w
fcvt.w.s
fcvt.w.d
fcvt.s.d
fcvt.d.s
fcvt.d.l
fcvt.l.d
fmadd
fcvt.s.l
fcvt.l.s
fmsub
frecip
frsqrt
fcmp
fmult
fadd
fsqrt
fsub
fdiv
the
Test/Breakpoint
Repeat Rates
single/double
Latency
21/36
21/36
21/36
38/68
4/5
4/5
4/5
4
4
4
6
6
4
4
4
4
4
4
4
1
1
1
facility,
single/double
Repeat Rate
19/34
19/34
19/34
36/66
1/2
1/2
1/2
1
1
1
3
3
1
1
1
1
1
1
1
1
1
1
and
the