act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 5

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

view of the processors operation however since the
out-of-order completion of loads, stores, and long latency
floating-point operations can result in there being even
more instructions in process than what is shown.
and branches result in some of the instruction slots being
occupied by NOPs.
Integer Unit
implements the MIPS IV Instruction Set Architecture, and
is therefore fully upward compatible with applications that
run on processors such as the R4650 and R4700 that
implement the earlier generation MIPS III Instruction Set
Architecture. Additionally, the ACT 7000ASC includes
two implementation specific instructions not found in the
baseline MIPS IV ISA, but that are useful in the embedded
market place. Described in detail in a later section of this
datasheet,
multiply-accumulate and three-operand integer multiply.
general purpose 64-bit registers, the HI/LO result registers
for the two-Pipeline operand integer multiply/divide
operations, and the program counter, or PC. There are two
separate execution units, one of which can execute
function, or F, type instructions and one which can execute
memory, or M, type instructions. See above for a
description of the instruction types and the issue rules. As
a special case, integer multiply/divide instructions as well
as their corresponding MFHi and MFLo instructions can
only be executed in the F type execution unit. Within each
execution unit the operational characteristics are the same
as on previous MIPS designs with single cycle ALU
operations (add, sub, logical, shift), one cycle load delay,
and an autonomous multiply/divide unit.
Register File
registers with register location (r0) hard wired to zero
value. These registers are used for scalar integer operations
and address calculation. In order to service the two integer
execution units, the register file has four read ports and two
write ports and is fully bypassed both within and between
the two execution units to minimize operation latency in
the pipeline.
ALU
each consisting of an integer adder/subtractor, a logic unit,
and a shifter. Table 3 shows the functions performed by the
ALU’s for each execution unit. Each of these units is
optimized to perform all operations in a single processor
cycle.
Note that instruction dependencies, resource conflicts,
Like the ACT 52xx family, the
The ACT 7000ASC integer unit includes thirty-two
The ACT 7000ASC has thirty-two general purpose
The ACT 7000ASC has two complete integer ALU’s
SCD7000A Rev B
these
instructions
ACT 7000ASC
are
integer
5
Integer Multiply/Divide
multiply/divide unit optimized for high-speed multiply and
multiply-accumulate operations. The multiply/divide unit
resides in the F type execution unit. Table 4 shows the
performance of the multiply/divide unit on each operation.
multiply or divide operation be placed in the Hi and Lo
registers. These values can then be transferred to the
general purpose register file using the Move-from-Hi and
Move-from-Lo (MFHI/MFLO) instructions.
instructions, the ACT 7000ASC also implements the
3-operand multiply instruction, MUL. This instruction
specifies that the multiply result go directly to the integer
register file rather than the Lo register. The portion of the
multiply that would have normally gone into the Hi register
is discarded. For applications where it is known that the
upper half of the multiply result is not required, using the
MUL instruction eliminates the necessity of executing an
explicit MFLO instruction.
multiply-add instructions MAD/MADU. This instruction
multiplies two operands and adds the resulting product to
the current contents of the Hi and Lo registers. The
multiply-accumulate operation is the core primitive of
almost all signal processing algorithms allowing the
ACT 7000ASC to eliminate the need for a separate DSP
engine in many embedded applications.
DIV, DIVD
DMULTU
MULT/U,
DMULT,
Shifter
Opcode
Adder
MAD/U
Table 4 – Integer Multiply / Divide Operations
DDIVU
Logic
DDIV,
Unit
The ACT 7000ASC has a single dedicated integer
The baseline MIPS IV ISA specifies that the results of a
In addition to the baseline MIPS IV integer multiply
Also included
MUL
logic, moves, zero
Table 3 – ALU Operations
Operand
16 bit
32 bit
16 bit
32 bit
non zero shift
Size
any
any
any
shifts (nop)
add, sub
F Pipe
in the ACT 7000ASC
Latency
36
68
4
5
4
5
9
non zero shift, store
logic, moves, zero
Repeat
Rate
add, sub, data
address add
36
68
shifts (nop)
3
4
3
4
8
M Pipe
align
Cycles
Stall
are
0
0
2
3
0
0
0
the