act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 4

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

illustrates the basics of the instruction issue mechanism.
M pipe instruction can be issued concurrently but that two
M pipe or two F pipe instructions cannot be issued. Table 2
specifies more completely the instructions within each
class.
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
Figure 2 is a simplification of the pipeline section and
The figure illustrates that one F pipe instruction and one
SCD7000A Rev B
F Pipe
FP
2A-2D:
1A-2A:
1I-1R:
Figure 2 – Instruction Issue Paradigm
1l
1l
2W:
2R:
1D:
1A:
1A:
2A:
F Pipe IBus
2I:
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
M Pipe
2l
2l
FP
1R
1R
1l
1l
M Pipe IBus
Instruction
Dispatch
Cache
Unit
2R
2R
2l
2l
1A
1A
1R
1R
1l
1l
Integer
F Pipe
2R
2R
2A
2A
2l
2l
1D
1D
1A
1A
1R
1R
Integer
M Pipe
1l
1l
Figure 3 – Pipeline
2D
2D
2A
2A
2R
2R
2l
2l
one cycle
1W
1W
1D
1D
1R
1R
1A
1A
1l
1l
4
.
xor, shift, etc.
add, sub, or,
ACT 7000ASC, in combination with its low latency integer
execution units and high-throughput fully pipelined
floating-point execution unit, provides unparalleled
price/performance in computational intensive embedded
applications.
Pipeline
stages with state committing in the register write, or W,
pipe stage. The physical length of the floating-point
execution pipeline is actually seven stages but this is
completely transparent to the user.
ACT 7000ASC
simultaneously down both pipelines. As illustrated in the
figure, up to ten instructions can be executing
simultaneously. This figure presents a somewhat simplistic
2W
2W
2D
2D
2R
2R
2A
2A
2l
2l
The
The logical length of both the F and M pipelines is five
Figure 3 shows instruction execution within the
integer
Table 2 – Dual Issue Instruction Classes
1W
1W
1D
1D
1A
1A
1R
1R
symmetric
2W
2W
2D
2D
2R
2R
2A
2A
lw, sw, ld, sd,
mov, movc,
ldc1, sdc1,
fmov, etc.
load/store
when
1W
1W
1D
1D
1A
1A
superscalar
2W
2W
2D
2D
2A
2A
instructions
floating-point
fmult, fmadd,
fadd, fsub,
fdiv, fcmp,
fsqrt, etc.
1W
1W
1D
1D
capability
2W
2W
2D
2D
are
bCzT, bCzF,
beq, bne,
1W
1W
branch
j, etc.
of
issuing
2W
2W
the