MRF24J40-I MICROCHIP [Microchip Technology], MRF24J40-I Datasheet - Page 36

• Manufacturer Part Number: MRF24J40-I
• Manufacturer: MICROCHIP [Microchip Technology]

7.4.2
The RX buffer is cleared when the length byte of the
packet and the last byte of the FCS are read. Once both
of these values are read from the RX buffer, the buffer
will enable itself to receive another packet. Because
the LQI and RSSI values are appended to the end of
REGISTER 7-3:
7.5
The MRF24J40 receiver features a low IF architecture
and consists of an LNA, a pair of down conversion
mixers, polyphase channel filters, baseband limiter
amplifiers and RSSI technology. An ADC is used to
sample the RSSI value and the sampled data is stored
in a register from which the data can be read out via the
SPI bus. The local oscillator generation circuits (VCO,
PLL and buffers) are shared with the receiver and
DS39776A-page 34
MRF24J40
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
Transceiver
FREEING RECEIVE BUFFER SPACE
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
RXWRTBLK: Software Write to RX FIFO Address bit
1 = Writing to any RX FIFO address is enabled
0 = Writing to any RX FIFO address is disabled
CMDONLY: Command Packet Receive bit
1 = Only command packets are received, all other packets are filtered out
0 = All valid packets are received
DATAONLY: Data Packet Receive bit
1 = Only data packets are received, all other packets are filtered out
0 = All valid packets are received
BCNONLY: Beacon Packet Receive bit
1 = Only beacon packets are received, all other packets are filtered out
0 = All valid packets are received
RXFLUSH: Flush RX FIFO Address bit
1 = Flush the RX FIFO. Cleared by hardware.
0 = Previous flush complete
R/W-0
RXFLUSH: RECEIVE FIFO FLUSH REGISTER
r
W = Writable bit
‘1’ = Bit is set
R/W-0
r
Advance Information
RXWRTBLK CMDONLY
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
the packet after the FCS, it may be advisable to read
these values out of the RX buffer before reading the
FCS.
Alternatively, it is possible to clear the RX buffer by
flushing it. This is done through the RXFLUSH register.
transmitter. The Low Noise Amplifier (LNA) features a
differential input for high performance. The RX/TX
switch is integrated and LNA input and Power Amplifier
(PA) output share the same pins. A common external
matching network and single-ended to differential con-
version is required. The transmitter features a direct
conversion architecture and has a 0 to -38.75 dBm out-
put power. The output power adjustment is in 1.25 dB
step. The TX gain is programmed by the SPI bus.
DATAONLY
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
BCNONLY
R/W-0
RXFLUSH
W-0
bit 0