as4lc4m16 Austin Semiconductor, Inc., as4lc4m16 Datasheet - Page 3

• Manufacturer Part Number: as4lc4m16
• Description: Extended Data Out Edo Dram
• Manufacturer: Austin Semiconductor, Inc.

GENERAL DESCRIPTION
random-access memory device containing 67,108,864 bits and
designed to operate from 3V to 3.6V. The device is functionally
organized as 4,194,304 locations containing 16 bits each. The
4,194,304 memory locations are arranged in 4,096 rows by 1,024
columns. During READ or WRITE cycles, each location is
uniquely addresses via the address bits: 12 row-address bits
(A0 - A11) and 10 column-address bits (A0 - A9). In addition,
both byte and word accesses are supported via the two CAS\
pins (CASL\ and CASH\).
control functions (e.g., latching column addresses or selecting
CBR REFRESH) is such that the internal CAS\ signal is
determined by the first external CAS\ signal (CASL\ or CASH\)
to transition LOW and the last to transition back HIGH. The
CAS\ functionality and timing related to driving or latching data
is such that each CAS\ signal independently controls the
associated either DQ pins.
AS4LC4M16
Rev. 1.1 6/05
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic
The CAS\ functionality and timing related to address and
FIGURE 1: WORD and BYTE WRITE Example
Austin Semiconductor, Inc.
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column address is latched by CAS\. This device provides
EDO-PAGE-MODE operation, allowing for fast successive data
operations (READ, WRITE or READ-MODIFY-WRITE) within
a given row.
order to retain stored data.
DRAM ACCESS
mentioned in the General Description. Use of both CAS\
signals resulted in a word access via the 16 I/O pins
(DQ0 - DQ15). Using only one of the two signals results in a
BYTE access cycle. CASL\ transitioning LOW selects an
access cycle for the lower byte (DQ0 - DQ7), and CASH\
transitioning LOW selects an access cycle for the upper byte
(DQ8-DQ15). General byte and word access timing is shown in
Figures 1 and 2.
The row address is latched by the RAS\ signal, then the
The 4 Meg x 16 DRAM must be refreshed periodically in
Each location in the DRAM is uniquely addressable, as
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4LC4M16
DRAM
DRAM
DRAM
DRAM
DRAM