as4lc4m16 Austin Semiconductor, Inc., as4lc4m16 Datasheet

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... MARKINGS None 25ns 13ns 8ns 30ns 15ns 10ns 1 AS4LC4M16 PIN ASSIGNMENT (Top View) 50-Pin TSOP (DG) Configuration 4 Meg x 16 Refresh 4K Row Address A0-A11 Column Addressing A0-A9 For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

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... Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... DQ7), and CASH\ transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... OE\ can be brought LOW or HIGH while CAS\ and RAS\ are LOW, and the DQs will transition between valid data and High- Z. Using OE\, there are two methods to disable the outputs and Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. FIGURE 3: OE\ Control of DQs FIGURE 4: WE\ Control of DQs AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... RAS\ only or burst CBR refresh then a burst refresh using t (MIN) is required. RC NOTES: *64ms for IT version, 32ms for XT version. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 RE- RASS . This delay allows for the completion RPS . ...

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... Exposure to absolute maximum rating conditions for extended periods may affect reliability. SYM +0.3V +0.3V DRAM DRAM DRAM DRAM DRAM AS4LC4M16 MIN MAX UNITS -0.3 0 µ µA 2.4 --- V --- 0.4 V Austin Semiconductor, Inc ...

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... I CC3 [MIN CC4 = t [MIN CC5 [MIN]) I CC6 [MIN CC7 = 125µS RC (MIN) RASS I CC8 8 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 1,2,3,5 MAX MAX UNITS 1.5 1 165 150 mA 125 120 mA 165 150 mA 165 150 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

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... OEP OES OFF ORD Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 UNITS NOTES 30 ...

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... WHZ WPZ WRH WRP Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 5,6,7,8,9,10,11,12 MAX UNITS NOTES µ 14 16 22, 23 ...

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... Last rising CASx\ edge to next cycles last rising CASx\ edge. 34. Last CASx LOW. , and t must always RAC CAC *64ms for IT version, 32ms for XT version. 11 AS4LC4M16 (MAX) defines the time at which the output achieves , and t are not restrictive operating RWD AWD CWD applies to EARLY WRITE cycles ...

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... Self refresh and extended refresh for the device requires that at least 4,096 cycles be completed every 128ms. 38. Self refresh version on IT temp parts only. AS4LC4M16 Rev. 1.1 6/ for a pulse width £ 12 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

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... Austin Semiconductor, Inc. NOTES referenced from rising edge of RAS\ or CAS\, whichever occurs last. OFF AS4LC4M16 Rev. 1.1 6/05 READ CYCLE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. AS4LC4M16 Rev. 1.1 6/05 EARLY WRITE CYCLE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. (LATE WRITE and READ-MODIFY-WRITE cycles) AS4LC4M16 Rev. 1.1 6/05 READ-WRITE CYCLE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. EDO-PAGE-MODE READ CYCLE NOTES (MAX) = 80,000ns for XT temperature version. RASP AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. EDO-PAGE-MODE EARLY WRITE CYCLE NOTES (MAX) = 80,000ns for XT temperature version. RASP AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) NOTES (MAX) = 80,000ns for XT temperature version. RASP AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) NOTES (MAX) = 80,000ns for XT temperature version. RASP AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. AS4LC4M16 Rev. 1.1 6/05 READ CYCLE (with WE\-controlled disable) 20 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

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... OE\ = DON’T CARE) NOTES: 1. End of first CBR REFRESH cycle. AS4LC4M16 Rev. 1.1 6/05 RAS\-ONLY REFRESH CYCLE (OE\ and WE\ = DON’T CARE) CBR REFRESH CYCLE 21 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

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... NOTES HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE\ is LOW and OE\ is HIGH. AS4LC4M16 Rev. 1.1 6/05 HIDDEN REFRESH CYCLE (WE\ = HIGH; OE\ = LOW) 22 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 1 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

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... RAS\ remains LOW, the DRAM will enter self refresh mode. RASS 2. Once t is satisfied, a complete burst of all rows should be executed if RAS\-only or burst CBR refresh is used. RPS AS4LC4M16 Rev. 1.1 6/05 SELF REFRESH CYCLE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 23 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. MECHANICAL DEFINITIONS AS4LC4M16 Rev. 1.1 6/05 (Package Designator DG) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 24 DRAM DRAM DRAM DRAM DRAM AS4LC4M16 ...

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... Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS4LC4M16DG-6S/XT Device Number AS4LC4M16 AS4LC4M16 *AVAILABLE PROCESSES XT = Industrial Temperature Range IT = Industrial Temperature Range OPTION DEFINITIONS S = Self Refresh AS4LC4M16 Rev. 1.1 6/05 Package Speed Options Type - +125 o - +85 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...