as4lc4m16 Austin Semiconductor, Inc., as4lc4m16 Datasheet - Page 11

• Manufacturer Part Number: as4lc4m16
• Description: Extended Data Out Edo Dram
• Manufacturer: Austin Semiconductor, Inc.

AS4LC4M16
Rev. 1.1 6/05
NOTES:
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
Specified values are obtained with minimum cycle time and the
outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle
time at which proper operation over the full temperature range
is ensured.
6. An initial pause of 100µs is required after power-up, followed
by eight RAS\ refresh cycles (RAS\-ONLY or CBR with WE\
HIGH), before proper device operation is ensured. The eight
RAS\ cycle wake-ups should be repeated any time the t
refresh requirements is exceeded.
7. AC characteristics assume t
8. V
timing of input signals. Transition times are measured between
V
9. In addition to meeting the transition rate specification, all
input signals must transit between V
and V
10. If CAS\ and RAS\ = V
11. If CAS\ = V
valid READ cycle.
12. Measured with a load equivalent to two TTL gates and
100pF; and V
13. If CAS\ is LOW at the falling edge of RAS\, output data will
be maintained from the previous cycle. To initiate a new cycle
and clear the data-out buffer, CAS\ must be pulsed HIGH
for t
14. The t
was specified as a reference point only. If t
the specified t
exclusively by t
without the t
15. The t
was specified as a reference point only. If t
the specified t
exclusively by t
without the t
be met.
16. Either t
IH
CC
IH
and V
CP
IH
(MIN) and V
.
is dependent on output loading and cycle rates.
) in a monotonic manner.
RAD
RCD
IL
RCH
(or between V
RCD
RAD
(MAX) limit is no longer specified. t
(MAX) limit is no longer specified. t
OL
RCD
RAD
or t
= 0.8V and V
CAC
AA
IL
limit, t
(MAX) limit, t
(MAX) limit, then access time was controlled
(MAX) limit, then access time was controlled
, data output may contain data from the last
RRH
IL
(t
(t
RAC
(MAX) are reference levels for measuring
RAC
must be satisfied for a READ cycle.
AA
and t
IH
[MIN] no longer applied). With our
IL
and t
, data output is High-Z.
and V
OH
CC
CAC
T
SS
Austin Semiconductor, Inc.
CAC
= 2.5ns.
AA
= 2V.
.
= +3.3V; f = 1 MHz; T
, t
IH
no longer applied). With or
must always be met.
RAC
).
IH
and V
, and t
RAD
RCD
IL
CAC
was greater than
was greater than
(or between V
must always
RCD
RAD
A
(MAX)
(MAX)
= 25°C.
REF
IL
11
17. t
the open circuit condition and is not referenced to V
18. t
parameters. t
t
data output will remain an open circuit throughout the entire
cycle. t
cycles. Meeting these limits allows for reading and disabling
output data and then applying input data. OE\ held HIGH and
WE\ taken LOW after CAS\ goes LOW results in a LATE WRITE
(OE\-controlled) cycle. t
applicable in a LATE WRITE cycle.
19. These parameters are referenced to CAS\ leading edge in
EARLY WRITE cycles and WE\ leading edge in LATE WRITE
or READ-MODIFY-WRITE operations are not possible.
20. If OE\ is tied permanently LOW, LATE WRITE, or READ-
MODIFY-WRITE operations are not possible.
21. A HIDDEN REFRESH may also be performed after a WRITE
cycle. In this case, WE\ is LOW and OE\ is HIGH.
22. RAS\-ONLY REFRESH that all 4,096 rows of the device be
refreshed at least once every 64ms.
23. CBR REFRESH for the device requires that at least 4,096
cycles be completed every 64ms.
24. The DQs go High-Z during READ cycles once t
occur. If CAS\ stays LOW while OE\ is brought HIGH, the DQs
will go High-Z. If OE\ is brought back LOW (CAS\ still LOW),
the DQs will provide the previous read data.
25. LATE WRITE and READ-MODIFY-WRITE cycles must
have both t
order to ensure that the output buffers will be open during the
WRITE cycle. If OE\ is taken back LOW while CAS\ remains
LOW, the DQs will remain open.
26. Column address changed once each cycle.
27. The first CAS\ edge to transition LOW.
28. Output parameter (DQx) is referenced to corresponding CAS\
input; DQ0 - DQ7 by CASL\ and DQ8 - DQ15 by CASH\.
29. Each CASx\ must meet minimum pulse width.
30. The last CASx\ edge to transition HIGH.
31. Last falling CASx\ edge to first rising CASx\ edge.
32. Last rising CASx\ edge to first falling CASx\ edge.
33. Last rising CASx\ edge to next cycles last rising CASx\
edge.
34. Last CASx\ to go LOW.
*64ms for IT version, 32ms for XT version.
WCS
OFF
WCS
> t
WCS
(MAX) defines the time at which the output achieves
RWD
, t
RWD
(MIN), the cycle is an EARLY WRITE cycle and the
OD
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
, t
AWD
and t
, t
WCS
AWD
, and t
OEH
applies to EARLY WRITE cycles. If
, and t
met (OE\ HIGH during write cycle) in
CWD
WCS
CWD
define READ-MODIFY-WRITE
, t
Notes continued on next page.
RWD
are not restrictive operating
AS4LC4M16
, t
CWD
, and t
DRAM
DRAM
DRAM
DRAM
DRAM
AWD
OD
OH
or tOFF
or V
are not
OL
.