hy5ps1g831l-y6 Hynix Semiconductor, hy5ps1g831l-y6 Datasheet - Page 73

• Manufacturer Part Number: hy5ps1g831l-y6
• Description: Ddr2 Sdram - 1gb
• Manufacturer: Hynix Semiconductor

Rev 0.2 / Apr. 2004
7. AC Timing Specifications
7.1 Timing Parameters by Speed Grade
DQ output access time
from CK/CK
DQS output access time
from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup
time
Control & Address input
pulse width for each input
DQ and DM input pulse
width for each input
Data-out high-impedance
time from CK/CK
DQS low-impedance time
from CK/CK
DQ low-impedance time
from CK/CK
DQS-DQ skew for DQS
and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time
from DQS
Write command to first
DQS latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK
setup time
DQS falling edge hold time
from CK
Mode register set
command cycle time
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
tHZ
tLZ
(DQS)
tLZ
(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
Symbol
min(tCL,
tAC min
tQHS
2*tAC
tHP -
5000
tCH)
WL -
-600
-500
0.45
0.45
0.35
0.25
0.35
0.35
min
DDR2-400 3-3-3
400
400
min
0.6
0.2
0.2
2
-
-
-
tAC max
tAC max
tAC max
+600
+500
WL +
max
0.55
0.55
8000
0.25
350
450
-
-
-
-
-
-
-
-
-
-
-
min(tCL,
tAC min
tQHS
2*tAC
tHP -
3750
tCH)
WL -
DDR2-533 4-4-4
0.45
0.45
0.25
0.35
0.35
min
-500
-450
350
350
0.35
min
0.6
0.2
0.2
2
-
-
-
+500
+450
8000
max
WL +
0.55
0.55
max
max
max
0.25
tAC
tAC
tAC
300
400
-
-
-
-
-
-
-
-
-
-
-
min(tCL,
tAC min
tQHS
2*tAC
3000
tHP -
tCH)
WL -
DDR2-667 5-5-5
-450
-400
0.45
0.45
0.25
0.35
0.35
min
300
300
0.35
min
0.6
0.2
0.2
2
-
-
-
HY5PS1G431(L)F
HY5PS1G831(L)F
+450
+400
8000
max
WL +
0.55
0.55
max
max
max
0.25
tAC
tAC
tAC
tbd
tbd
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
11,12
Note
6,7,8
6,7,8
15
13
12
75