hy5ps1g831l-y6 Hynix Semiconductor, hy5ps1g831l-y6 Datasheet - Page 54

• Manufacturer Part Number: hy5ps1g831l-y6
• Description: Ddr2 Sdram - 1gb
• Manufacturer: Hynix Semiconductor

Rev 0.2 / Apr. 2004
2.10 Asynchronous CKE Low Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asyn-
chronously drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of array. If
this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the clocks.
Stable clocks must exist at the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-initial-
ized (steps 4 thru 13) as described in initializaliation sequence. DRAM is ready for normal operation after the ini-
tialization sequence. See AC timing parametric table for tDelay specification
CK#
CKE
CK
CKE asynchronously drops low
tCK
tDelay
Clocks can be turned
off after this point
Stable clocks
HY5PS1G431(L)F
HY5PS1G831(L)F
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