SC220 ZARLINK [Zarlink Semiconductor Inc], SC220 Datasheet - Page 21

• Manufacturer Part Number: SC220
• Description: XpressFlow 2020 Ethernet Routing Switch Chipset
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

XpressFlow-2020 Series –
Ethernet Switch Chipset
2.4 XpressFlow Bus Interface
t
t
t
t
2.4.1 Pin Description
© 1998 Vertex Networks, Inc.
1999
Vertex Networks’ optimized XpressFlow Bus
architecture
Provides 1G bps switching bandwidth
Full multi bus master structure
Allows XpressFlow Engine to communicate
with Access Controllers via a message pass-
ing protocol
Command Messages for passing control
information between devices
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ[8:1]# CMOS
S_GNT[8:1]#
S_OVLD#
S_CLK
Symbol
P
R
E
I/O-OD
I/O-OD
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
CMOS
CMOS
Output
CMOS
Output
CMOS
L
Type
Input
Input
I
M
Name & Functions
Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Note: During the system RESET period, Data Bit [31:28] are used as
Message Envelope – encompasses the entire period of a message
transfer. Targets use the leading edge of this signal to detect the be-
ginning of a message transfer, and to decode the message header for
the intended target(s).
End of Frame – only used by frame data transfer messages to identify
the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.
Initiator Ready – a normal true signal. When negated, it indicates the
initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.
Target Abort – when asserted, the target had aborted the reception of
current message on the bus.
High Priority Request – indicates one or more Bus Requester is re-
questing for high priority message transfer.
Bus Request [8:1] – Bus Request signals from Access Controllers to
Bus Access Arbitrator in XpressFlow Engine
Bus Grant [8:1] – Bus Grant signals from Bus Arbitrator to Bus Re-
questers
Bus Overload – when asserted all data forwarding bus bandwidth has
been allocated. Cannot support additional load for data forwarding traf-
fic
XpressFlow Bus Clock – 33MHz system clock
I
N
A
Processor Interface Configuration bit [0:3]
R
Y
I
20
t
t
N
Built-in intelligent bus load regulator for data
traffic balancing
Provides centralized bus arbitration with two
level request priorities
F
Data Messages for forwarding an Ethernet
frame from receiving port to transmission
port
High priority for Data Messages
Low priority for Command Messages
O
R
M
A
T
I
XpressFlow Engine
O
N
Rev. 4.5 – February
SC220