SC220 ZARLINK [Zarlink Semiconductor Inc], SC220 Datasheet - Page 16

• Manufacturer Part Number: SC220
• Description: XpressFlow 2020 Ethernet Routing Switch Chipset
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

XpressFlow-2020 Series –
Ethernet Switch Chipset
2.3
t
t
2.3.1
© 1998 Vertex Networks, Inc.
1999
Supports various industry standard micro-
processors including:
Easily adapts to other industry standard CPUs
Intel 186/486 family or equivalent
Motorola MPC series embedded processors
Management Bus Interface
P_C[4:0]
P_A[11:1]
P_D[15:0]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
P_CLK
P_RSTIN#
P_RSTOUT
Pin Description
Note:
Symbol
P
R
•
•
E
CMOS Input Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the proc-
TTL In
(5VT)
TTL I/O-TS
(5VT)
TTL In
(5VT)
TTL
put (5VT)
TTL Out-
OD
TTL Out-OD Bus Size 16 – response to bus master that the SC-201 only supports 16-bit data bus width.
TTL In
(5VT)
TTL Out-
put
TTL In
(5VT)
TTL In-ST
(5VT)
CMOS
Output
Output signal with programmable polarity.
L
Type
I
In-
M
Name & Functions
essor configuration. By using external weak pull-up or -down resistors, they define the External
Management Bus Interface Configuration. These inputs are sampled at the trailing edge of the
Reset cycle.
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
Address Bus Bit [11:1] – I/O port address
Data Bus Bit [15:0] – a 16-bit synchronous data bus.
Address Strobe – indicates valid address is on the bus
Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
Data Ready – timing indicates for bus data valid
Chip Select – indicates the XpressFlow Engine is the target for the current bus operation.
Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable via
chip configuration register.
CPU Clock – 1X Clock for the others
Power Up Reset Input – Asynchronous Reset Input from either Power-Up Reset circuit or from
Switch Manager CPU (except 386)
Synchronous Reset Output – Synchronous Reset Output for i386 family as the Switch Manager
CPU
I
Lo
Hi
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Data Bus width – 16-bit or 32-bit
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
C[1]=Low
C[1]=High
N
A
CPU Clock
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
1X Clock
2x Clock
C[0]
R
P_R/W# is used for PowerPC or other similar processors.
P_W/R# is used for 386, 486 or other similar processors
Y
I
Little Endian
15
t
t
t
t
Byte Order
Big Endian
N
C[1]
Provides separate Address and Data bus
Supports Big & Little Endian byte ordering
Supports 16- or 32-bit Data Bus
Provides a single interrupt signal to Switch
Manager CPU
F
O
R
P_R/W#
P_W/R#
RWC
C[2]
M
A
T
Bus Width
I
16-bit
32-bit
XpressFlow Engine
C[3]
O
N
Rev. 4.5 – February
RDY Timing
Normal
Early
C[4]
SC220