bt865a Conexant Systems, Inc., bt865a Datasheet - Page 16

• Manufacturer Part Number: bt865a
• Description: Ycrcb To Ntsc/pal Digital Video Encoder
• Manufacturer: Conexant Systems, Inc.

Circuit Description
1.4
1.4.1
1-6
HSYNC* Timing
Master Mode
There are two HSYNC* timing modes in master mode; default mode and variable
HSYNC* timing mode. The variable HSYNC* timing mode is enabled by setting
ADJHSYNC high. This mode allows the user to specify the placement of the falling
and rising edges of HSYNC* by using the HSYNCF and HSYNCR registers,
respectively. The values of registers HSYNCF and HSYNCR correspond to the pixel
count of the internal pixel counter (see
be zero and cannot be equal. Values must also be less than or equal to the total
horizontal resolution given in
rising edge occurs, the part will not automatically reset, but will wait until the pixel
counter reaches the specified HSYNCR value. The placement of the analog horizontal
sync pulse is fixed relative to the internal pixel counter, therefore when the rising and
falling edges of HSYNC* are moved, the pipeline delay between the HSYNC* pulse
and the analog horizontal sync pulse is altered. In this mode, the pipeline delay from
HSYNC* to analog sync out is 40–(2*HSYNCF) if SYNCDLY = 0, and 41–
(2*HSYNCF) if SYNCDLY = 1. In the default HSYNC* timing mode, the placement
of the edges of the HSYNC* pulse are fixed, with the exception of the one clock delay
available through the register SYNCDLY. In this mode, the pipeline delay from
HSYNC* to analog sync out is 40 clocks if SYNCDLY = 0, and 41 clocks if
SYNCDLY = 1. In the default mode, the delay from internal horizontal pixel counter
reset to the falling edge of HSYNC* is 2 clocks.
Conexant
Table
1-2. If the internal pixel counter resets before the
Figure
1-3). HSYNCF and HSYNCR cannot
Bt864A/Bt865A Data Sheet
100138C
02/17/03