cxd3152ar Sony Electronics, cxd3152ar Datasheet - Page 19

no-image

cxd3152ar

Manufacturer Part Number
cxd3152ar
Description
Signal Processor Lsi For Single-chip Ccd B/w Camera
Manufacturer
Sony Electronics
Datasheet
Timing Chart
Horizontal Direction Timing
Vertical Direction Timing
2MCK:
MCK:
MCKO:
CCDIN:
SHP:
SHD:
cblk:
CSYNC:
A_CLP:
D_CLP:
DOUT[7:0]: 8-bit digital output signal
ANA:
HD:
cblk:
CSYNC:
A_CLP:
D_CLP:
CCDIN:
DOUT[7:0]: 8-bit digital output signal
Master clock input for the CXD3152AR
Internal reference clock produced by dividing the input reference clock (2MCK) in half.
Latch clock for digital output signal (Inverted MCK signal)
Imaging signal from CCD
Precharge level sampling pulse input
Video level sampling pulse input
Internal composite blanking pulse (for VIDEO output signal)
Composite sync pulse input (in phase for CSYNC_IN and the VIDEO output signal)
Internal pulse for analog clamp
Internal pulse for digital clamp
Analog output signal
Internal horizontal sync signal
Internal composite blanking pulse (for VIDEO output signal)
Composite sync pulse input (in phase for CSYNC_IN and the VIDEO output signal)
Internal pulse for analog clamp
Internal pulse for digital clamp
Video signal from the CCD
– 19 –
CXD3152AR

Related parts for cxd3152ar