cxd3152ar Sony Electronics, cxd3152ar Datasheet
cxd3152ar
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cxd3152ar Summary of contents
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... Signal Processor LSI for Single-chip CCD B/W Camera Description The CXD3152AR is a digital signal processor LSI for CCD black-and-white cameras. In addition to the CDS and AGC circuits of conventional analog signal processor LSI, this chip also features the ease of use and functions of digital signal processing. ...
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... COMP CVREF, PREF GAIN REGRES SCL, SDA, CSYNC_IN DGC AGC, 2 BLCW1, EIA CCD, 2MCKI SHD SHP – 2 – CXD3152AR CHARA MIRROR REFL REFH, REFLIN REFHIN, MONITOR ...
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... The gain can be set by the register. • Blemish detection and compensation function total of 10 white point blemishes can be detected and compensated during dark signal. Blemish addresses can be read out by serial communication. • Digital output 8-bit digital signal output – 3 – CXD3152AR ...
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... Supports backlight compensation Registers 2 • bus Various register settings: <SCL, SDA, REGRES> Slave address: [A6:A0] = 0011111 (b) Related pins: <SCL, SDA, REGRES> • External EEPROM An EEPROM which supports the I Register values can be automatically read out during power-on bus can be connected. – 4 – CXD3152AR ...
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... DD 57 EIA 58 CCD 59 CSYNC_IN 60 BLCW1 61 BLCW2 62 SHD 63 SHP 64 GOUT – 5 – CXD3152AR MCKPHS 30 GAMMA2 29 GAMMA1 28 APCON 27 MIRROR 26 DGC 25 AGC (3.3V DEFECT 22 TEST (3.3V) DD ...
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... Digital power supply (3.3V AGC I Analog gain switching 0: Fixed, 1: Auto 26 DGC I Digital gain switching 0: Fixed, 1: Auto 27 MIRROR I Mirror inversion switching 0: Standard, 1: Mirror 28 APCON I Aperture correction switching 0: Off GAMMA1 I Gamma correction characteristics switching 00: 0.45, 01: 0.6 (register setting), 10: 1.0, 11: S curve 30 GAMMA2 I Description – 6 – CXD3152AR ...
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... CCD number of horizontal pixels switching 58 CCD I 0: 510H system, 1: 760H system 59 CSYNC_IN I Composite sync input BLCW1 Backlight compensation window switching 60 I 00: Full-screen photometry, 01: Bottom photometry 61 BLCW2 I 10: Center photometry, 11: Bottom + center photometry 62 SHD I Data block sampling pulse input Description – 7 – CXD3152AR ...
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... AGC gain control voltage output (DAC output) 64 GOUT O(A) Connect to GND via an approximately 0.1µF capacitor. Note 1) Asterisks ( ) indicate that either 3.3V or 5.0V input is possible. Note 2) The I/O column symbol meanings are as follows Digital input O : Digital output I/O : Digital input/output I(A) : Analog input O(A) : Analog output P : Power supply/GND Description – 8 – CXD3152AR ...
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... 4mA — – high impedance output –10 Conditions Min. 0.7V DD CMOS supported — – – 9 – CXD3152AR (V = 3.0 to 3.6V 0V Applicable Typ. Max. Unit pins — — — 0. — — — 0.15V V ...
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... CXD3152AR = 50pF) L Typ. Max. Unit — — ns — — ns — — — ns — — ns — — — ns — — ...
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... Master Clock Generation Timing (1) MCKPHS = Low 2MCKI thd1 CSYNC_IN MCKO (2) MCKPHS = High 2MCKI tsu2 thd2 CSYNC_IN MCKO Video Signal Related Input/Output Timing MCKO CHARA tsu1 tdly1 tdly1 tdly2 tdly2 tsu3 thd3 – 11 – CXD3152AR tdly1 tdly2 tdly3 ...
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... Reset Timing REGRES bus Timing SCL thigh SDA (input) SDA (output) Analog Signal Processing Sampling Pulse Timing 2MCKI SHP tdly6 SHD ADCLK Note 1) When MCKPHS = Low tpor V IH tlow tsu4 thd4 Hi-Z tdly4 tdly7 tdly8 tdly8 – 12 – CXD3152AR trst tdly5 ...
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... ZERO 1.21 1.30 1.43 FULL 0 6.6 16.5 — — ±2.0 — — ±1.0 – 13 – CXD3152AR ( 3.3V 0V 25° Unit Test conditions Bits MSPS LSB DC accuracy LSB DC accuracy ( 3.3V 0V 25° Unit Test conditions Bits MSPS mW ...
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... V 1.6 2.0 2.7 V 1.6 2.2 2.6 V 8.3 9.5 10.7 dB 1.6 2.1 2.7 V – 14 – CXD3152AR = 0V 25°C) SS Test conditions CAP1 output DC level CCDIN = 1.6V (DC) GOUT = 1.5V CAPA2 output DC level CCDIN = 1.6V (DC) GOUT = 1.5V YOUT output DC level CCDIN = 1.6V (DC) GOUT = 2.5V GCOF1 = V4 – CDSDC V4 = YOUT output DC level CCDIN = 1.6V (DC) GOUT = 1.5V GCOF2 = V5 – CDSDC V5 = YOUT output DC level CCDIN = 1.6V (DC) GOUT = 0.5V YOUT output gain ...
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... V DD Min. Typ. Max. 2.8 2.9 3.0 0.8 0.9 1 3.3V 0V 25° 2.0 2.5 3.0 3.3 – 15 – CXD3152AR 3 = 3.3V 0V 25° Unit Test conditions CAPB2 output DC level V SW1 = A, SW2 = A MONITOR output DC level V CLP = "H" SW1 = A, SW2 = A MONITOR output gain dB SW1 = B, SW2 = B (Note 1) YIN = S4 MONITOR output AC level ...
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... DD DC bias output pin of the gain control amplifier 1k 3.00V DC output (typ.) 10k 10k DC bias output pin of the CDS circuit 1.58V DC output (typ.) Clamp level (DC) input pin of the clamp circuit for A/D conversion 2.73V DC input (typ.) – 16 – CXD3152AR Description ...
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... DC output (typ Low reference output pin for ADC Voltage follower output 16 0.80V DC output (typ bias output pin for ADC 1.55V DC output (typ D/A converter negative output 0 to 1.24V output 38 D/A converter positive output 1.24V output – 17 – CXD3152AR Description ...
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... Note) For the power supply names in the equivalent circuits, refer to the symbols in the Pin Description. Equivalent circuit – 18 – CXD3152AR Description DAC reference voltage generation pin 1.32V DC output (typ.) DAC reference voltage output pin 1.32V DC output (typ.) DAC phase compensation pin 2.18V DC output (typ.) ...
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... Timing Chart Horizontal Direction Timing 2MCK: Master clock input for the CXD3152AR MCK: Internal reference clock produced by dividing the input reference clock (2MCK) in half. MCKO: Latch clock for digital output signal (Inverted MCK signal) CCDIN: Imaging signal from CCD SHP: Precharge level sampling pulse input ...
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... The CXD3152AR performs serial communication between external EEPROM via the I communication with a PC, the PC is the master device and the CXD3152AR is the slave device. On the other hand, in communication with an EEPROM, the CXD3152AR is the master device and the EEPROM is the slave device ...
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... Note 1) The upper 7 bits of the slave address indicate the device address, while the lowermost bit indicates the R/W mode. (Read mode when this bit is high, and write mode when it is low.) Note 2) The CXD3152AR slave address is [A6:A0] = 0011111 (b). Note 3) ACK is the response acknowledgement signal, and the slave device goes to low. ...
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... EIA760 system = 89 (h) 6 CCIR760 system = 96 ( Gamma correction curve adjustment-1 1 Sets the intersection between the 1st approximation line (slope = 1) and the 2nd 2 approximation line (slope = 3). 3 Setting range – 28 – CXD3152AR Default R/W — ( ( (h) W ...
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... Setting range Gamma correction curve adjustment-5 2 Sets the intersection between the 5th approximation line (slope = 3/4) and the 6th 3 approximation line (slope = 1/2). 4 Setting range – 29 – CXD3152AR Default R (h) W ...
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... HAPCORE2), OUTPUT = 0 00 (h): Noise suppression off 7 03 (h): Maximum noise suppression level 0 Vertical aperture correction signal gain setting 1 The gain changes linearly from 0 ( (h (h): Maximum gain – 30 – CXD3152AR Default R (h) 04 (h) W ...
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... Aperture correction signal coring level DGC link 1 setting 2 0x0: Coring off 0x1F: Maximum coring level Signal gain setting when GAMMA1 and GAMMA2 are set to 00 (gamma = 0.45 – 31 – CXD3152AR Default R ( ( (h) W ...
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... Signal gain setting when GAMMA1 and GAMMA2 are set to 11 (gamma = Pedestal level setting 2 The pedestal level changes linearly from (h): Low 17 (h): 7.5 IRE 4 3F (h): High – 32 – CXD3152AR Default R (h) W ...
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... Externally input 1-bit character signal gain setting 2 00 (h): –85 IRE 20 (h): ± (h): +85 IRE White clip level setting Video signal minus component clip level setting – 33 – CXD3152AR Default R (h) W ...
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... Setting range Aperture correction signal added position setting 0 0: After gamma correction, 1: Before gamma correction Reference level setting for auto gain control 3 integral value – 34 – CXD3152AR Default R (h) W ...
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... Analog gain control (AGC) maximum gain limiter 2 setting (Sets the upper 7 bits for gain signal generating 8-bit DAC. The lowest digit is "0".) 3 Valid when AGC = 1 00 (h) : Min (h) : Max – 35 – CXD3152AR Default R (h) W ...
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... Insensitive range setting (0: Narrow, 1: Wide) 3 Digital clamp operation mode setting (011: V period, 100: H period) 6 bit is also used Digital clamp function ON/OFF (= 1) 6 Digital clamp operation mode setting 7 – 36 – CXD3152AR Default R ( ...
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... Digital clamp insensitive range setting Maximum number of registered blemishes setting Maximum 10 points – 37 – CXD3152AR Default R (h) W ...
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... D0: EVEN Y address offset data relative to ODD 3 0: Offset value 0, 1: Offset value 1 Fixed D2: Valid data/invalid data 5 0: Invalid data, 1: Valid data D3: Internal data/external data 6 0: External, 1: Internal dummy 7 – 38 – CXD3152AR Default R (h) R/W 00 (h) R/W 00 (h) 00 (h) R/W 00 (h) ...
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... DEF73 Omitted: Same as DEF03 7C (h) DEF81 Omitted: Same as DEF01 7D (h) DEF82 Omitted: Same as DEF02 7E (h) DEF83 Omitted: Same as DEF03 7F (h) DEF91 Omitted: Same as DEF01 80 (h) DEF92 Omitted: Same as DEF02 81 (h) DEF93 Omitted: Same as DEF03 bit Description – 39 – CXD3152AR Default R/W ...
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... Backlight compensation window switching 0 (Same function as BLCW1 and BLCW2 pins) 00: Full-screen photometry, 01: Lower photometry 1 10: Center photometry, 11: Lower + center photometry Register setting/pin setting selection 2 0: Pin setting, 1: Register setting – 40 – CXD3152AR Default R/W 00 (h) 00 ( ( (h) 00 (h) W ...
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... Pin setting, 1: Register setting Mirror inversion switching (Same function as MIRROR pin Standard, 1: Mirror Register setting/pin setting selection 1 0: Pin setting, 1: Register setting – 41 – CXD3152AR Default R/W 00 ( ( (h) 00 (h) W ...
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... Blemish compensation function switching (Same function as DEFECT pin Off Register setting/pin setting selection 1 0: Pin setting, 1: Register setting Video output DAC on/off 0 0: On, 1: Off – 42 – CXD3152AR Default R/W 00 ( ( (h) W ...
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... Register setting/pin setting selection 1 0: Pin setting, 1: Register setting 1-bit character signal input switching 0 (Same function as CHARA pin) Register setting/pin setting selection 1 0: Pin setting, 1: Register setting – 43 – CXD3152AR Default R/W 00 ( (h) 00 (h) W ...
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... Using the EEPROM The CXD3152AR can connect an external EEPROM which supports the I and from the EEPROM are performed from the PC master via the I can automatically read the user-set register values during power-on by writing the addresses and setting values for registers in the EEPROM. (At this time this IC is the master device and the EEPROM is the slave device ...
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... LQFP (PLASTIC) 12.0 0.2 10.0 0 0.08 0.18 – 0.03 0 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS – 45 – CXD3152AR 0.15 0.05 0.1 A 1.7 MAX EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g SPEC. 42 ALLOY Sn-Bi 5-18 m Sony Corporation ...