ade3700 STMicroelectronics, ade3700 Datasheet - Page 81

• Manufacturer Part Number: ade3700
• Description: Analog Lcd Display Engine For Xga And Sxga Resolutions
• Manufacturer: STMicroelectronics

ADE3700
2.21
DFT_TEST_MODE
DFT_MUX_OUT_MODE
DFT_FLOP_OUT_MODE
DFT_CLK_0UT_MODE
DFT_CLK_1_MODE
PWM_CTRL1
PWM_PERIOD_L
PWM_PERIOD_H
PWM_DUTY_L
PWM_DUTY_H
PWM_OVERLAP_L
PWM_OVERLAP_H
PWM_STEP_DELAY
PWM_CYCLES_PER_FRAME_L
PWM_CYCLES_PER_FRAME_H
Register Name
DFT Block
Register Name
0x0F00
0x0F01
0x0F02
0x0F03
0x0F04
Addr
Table 33: PWM Registers (Sheet 2 of 2)
0x01A1
0x01A2
0x01A3
0x01A4
0x01A5
0x01A6
0x01A7
0x01A8
0x01A9
0x01AA
Table 34: DFT Registers (Sheet 1 of 3)
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7:4]
[3]
[2]
[1]
[0]
[7:6]
[5:0]
[7:6]
[5:0]
[7:6]
[5:0]
[7:6]
Bits
[7:4]
[3:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
Lock 2
0x0 = max
0x3 = typical
0xF = min.
Lock gain (power of 2)
0x0 = max
0x6 = typical
0xF = min.
Period-2 in free-running mode, in XCLKs
Duty cycle of PWM in XCLKs
Non-overlap of PWMs in XCLKs
In smooth change mode, the number of
cycles skipped before the period/duty
registers are incremented/decremented
The number of cycles per frame in frame
lock mode when not using the internally
generated cycles per frame from a previous
free-running mode
enable output pin MFSR
clear output pin MFSR
bus
fout = selected clock / (2 ^ value)
pin
fout = selected clock / (2 ^ value)
Reserved
trigger video bus MFSR
output pin test override
Reserved
mux selector for output porta/b and syncs
Reserved
mux selector for synchronous digital debug
divide-by selector for clocks to OCLK pin
mux selector for clocks to OCLK pin
divide-by selector for clocks to CLKOUT
nd
order gain (power of 2)
Description
Description
DFT Block
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