ade3700 STMicroelectronics, ade3700 Datasheet - Page 24

• Manufacturer Part Number: ade3700
• Description: Analog Lcd Display Engine For Xga And Sxga Resolutions
• Manufacturer: STMicroelectronics

Sync Retiming (SRT)
24/89
SRTXK_COAST_VS_SEL
SRTXK_COAST_RISE_L
SRTXK_COAST_RISE_M
SRTXK_COAST_RISE_H
SRTXK_COAST_FALL_L
SRTXK_COAST_FALL_M
SRTXK_COAST_FALL_H
SRTIK_HS_CTRL
SRTIK_VS_SEL
Register Name
Table 8: Sync Retiming Registers (Sheet 2 of 2)
0x01EA
0x01EB
0x01ED
0x01EE
0x01F0
0x01F1
0x01E8
0x01E9
0x01EC
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[3]
[2:0]
[2]
[1:0]
[1:0]
[7:4]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:3]
[7:2]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0: posedge of selected vertical
1: negedge of selected vertical
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: Reserved
0x4: nc
0x5: nc
0x6: srt vsync (filtered vsync)
0x7: Reserved
trigger
trigger
the INCLK domain; depends on LLK phase
offset value.
0: posedge INCLK
1: negedge INCLK
the INCLK domain
0x0: LLPLL lock sync (normal)
0x1: ahsync pin
0x2: acsync pin
0x3: Reserved
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: srt vsync (filtered vsync)
Reserved
coast signal trigger edge
source select for coast vert sync trigger
rising edge of coast, in XCLKs from vsync
falling edge of coast, in XCLKs from vsync
Reserved
Resample clock edge to transfer hsync into
horz sync source select for resampling into
Reserved
vert sync source select for resampling
Description
ADE3700