ade3700 STMicroelectronics, ade3700 Datasheet - Page 19

• Manufacturer Part Number: ade3700
• Description: Analog Lcd Display Engine For Xga And Sxga Resolutions
• Manufacturer: STMicroelectronics

ADE3700
Register Name
LLK_PLL_CLEAR
LLK_PLL_CTRL
LLK_PLL_MFACTOR_L
LLK_PLL_MFACTOR_H
LLK_PLL_HPERIOD_L
LLK_PLL_HPERIOD_H
LLK_PLL_PHASE_RATE_INIT_0
LLK_PLL_PHASE_RATE_INIT_1
LLK_PLL_PHASE_RATE_INIT_2
LLK_PLL_PHASE_RATE_INIT_3
LLK_PLL_PHASE_RATE_INIT_WR
Table 7: Line Lock PLL Registers (Sheet 1 of 4)
0x0800
0x0801
0x0802
0x0803
0x0805
0x0806
0x0807
0x0808
0x0809
0x080A
0x0804
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:1]
[0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0280
0x0040
0x0
Default
Reserved
master reset
reset the PLL synthetic sync
reset PLL offset
reset PLL accumulator
reset the low pass filter
reset the PLL phase error
Reserved
zero clock delay enable
0: normal
1: diagnostic mode -- PLL uses only fine
error
0: normal
1: diagnostic -- coarse error is multiplied by
2
input hsync edge selection
0: rising edge
1: falling edge
sync on green input selection
0: composite sync (HSYNC pin)
1: sync on green (CSYNC pin)
0: normal
1: divide PLL clock by 2
0: normal
1: free-running mode
number of clocks in a line
pulse width of synthetic hsync
initial phase rate
fout = fxtal * 2
Reserved
When written to 1, the pll phase rate is
initialized with the initial phase rate
register. Self clearing.
27+NDIV
Description
/ phase_rate
Line Lock PLL
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