gc41c501g1-so24i CORERIVER Semiconductor, gc41c501g1-so24i Datasheet - Page 39

• Manufacturer Part Number: gc41c501g1-so24i
• Description: 4-bit Microcontrollers With Reduced 8051 Architecture
• Manufacturer: CORERIVER Semiconductor

ANL A, @DP
Appendix A : Instruction Set (4/19)
Binary Code
Description
Carry Flag
Operation
Example
Cycles
Bytes
ANL performs the bitwise logical-AND operation
between the indirect data memory and ACC.
The result is stored in Accumulator.
(A) ← (A) & M[DP]
Not affected.
1
1
; Assumes M[DP] contains 2
MOV A, #0xA ; Set ACC as 10.
ANL A, @DP
0000
1100
; The result, 2 is stored in ACC.
CALL addr
Binary Code
Description
Carry Flag
Operation
Example
Cycles
Bytes
Unconditionally calls a subroutine located at the
indicated 12-bit address. The instruction
increments the PC twice to obtain the address
of the following instruction, then push the
result onto the stack (low-order nibble first).
The stack pointer is incremented three times.
The destination address is obtained by
concatenating four low-order bits of the
opcode byte and the second byte of the
instruction.
(PC) ← (PC) + 2
(SP) ← (SP) + 1
M[SP] ← (PC
(SP) ← (SP) + 1
M[SP] ← (PC
(SP) ← (SP) + 1
M[SP] ← (PC
(PC) ← addr
Not affected.
2
2
CALL SUBR ; Call subroutine located
1111
ATOM1.0 Family
aaaa
; at the label SUBR.
3-0
7-4
11-8
)
)
)
aaaa
Preliminary
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