k9f2g08uxa Samsung Semiconductor, Inc., k9f2g08uxa Datasheet - Page 9
k9f2g08uxa
Manufacturer Part Number
k9f2g08uxa
Description
256m X 8 Bit Nand Flash Memory
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K9F2G08UXA.pdf
(44 pages)
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K9F2G08R0A
K9F2G08U0A
Figure 1. K9F2G08X0A Functional Block Diagram
Figure 2. K9F2G08X0A Array Organization
V
V
128K Pages
(=2,048 Blocks)
CC
SS
NOTE : Column Address : Starting Address of the Register.
2nd Cycle
CE
RE
WE
3rd Cycle
1st Cycle
4th Cycle
5th Cycle
Command
A
A
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
12
0
- A
- A
11
28
I/O 0
A
A
A
A
A
12
20
28
0
8
& High Voltage
CLE
2K Bytes
Page Register
Control Logic
2K Bytes
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
Generator
Register
I/O 1
A
A
A
A
*L
ALE
13
21
1
9
WP
I/O 2
A
A
A
A
*L
10
14
22
2
64 Bytes
64 Bytes
I/O 3
A
A
A
A
*L
11
15
23
3
9
I/O 4
A
A
A
*L
*L
16
24
I/O 0 ~ I/O 7
4
(2,048 + 64)Byte x 131,072
Global Buffers
Data Register & S/A
I/O Buffers & Latches
2,048M + 64M Bit
I/O 5
A
A
A
*L
*L
17
25
NAND Flash
5
8 bit
Y-Gating
ARRAY
1 Block = 64 Pages
(128K + 4k) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
1 Device = (2K+64)B x 64Pages x 2,048 Blocks
I/O 6
A
A
A
*L
*L
18
26
6
= (128K + 4K) Bytes
= 2,112 Mbits
I/O 7
A
A
A
*L
*L
FLASH MEMORY
19
27
7
Output
Driver
Column Address
Column Address
Row Address
Row Address
Row Address
V
V
CC
SS
I/0 7
I/0 0
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