k9f2g08uxa Samsung Semiconductor, Inc., k9f2g08uxa Datasheet - Page 42

• Manufacturer Part Number: k9f2g08uxa
• Description: 256m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F2G08R0A
K9F2G08U0A
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.
Figure 18. Read ID Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 19
below.
Figure 19. RESET Operation
Table 5. Device Status
R/B
I/O
CLE
CE
WE
ALE
RE
I/O
X
X
Operation mode
K9F2G08R0A
K9F2G08U0A
Device
90h
FFh
Device Code (2nd Cycle)
Address. 1cycle
00h Command is latched
00h
AAh
DAh
After Power-up
t
CLR
t
WHR
t
AR
t
CEA
t
REA
t
RST
3rd Cycle
Maker code
42
ECh
00h
10h
Device code
Device
Code
Waiting for next command
4th Cycle
3rd Cyc.
15h
95h
After Reset
FLASH MEMORY
4th Cyc.
5th Cycle
5th Cyc.
44h
44h