m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 22

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

SDRAM (Rev. 0.3)
[ Write Interrupted by Precharge ]
(tWR) is required between the last input data and the next PRE. This may require DQMU/DQML control
depending on the CLK frequency and tWR timing. See the example below.
[ Write Interrupted by Burst Terminate ]
write recovery time is not required and the bank remains active (Please see the waveforms below). The
WRITE to TERM minimum interval is one CLK.
Feb ‘97 Preliminary
A burst write operation can be interrupted by precharging (PRE) the same bank. Write recovery time
A burst terminate command TBST can be used to terminate a burst write operation. In this case, the
Command
Command
DQMU
DQML
DQMU
DQML
A0-7
CLK
A0-7
A8
BA
CLK
DQ
DQ
BA
A8
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Write
Dai0
Write
Dai0
Yi
0
0
Yi
0
0
Write Interrupted by Precharge (BL=4)
Write Interrupted by Burst Terminate (BL=4)
Dai1
Dai1
tWR
Dai2
MITSUBISHI ELECTRIC
TERM
PRE
0
0
M5M4V4S40CTP-12, -15
This data should be masked to satisfy tWR requirement.
tRP
ACT
Xb
Xb
0
MITSUBISHI LSIs
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