m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 18

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
BURST INTERRUPTION
[ Read Interrupted by Read ]
allows random column accesses. READ to READ interval is a minimum of one CLK.
[ Read Interrupted by Write ]
disabled two cycles automatically after WRITE assertion. Random column access is allowed.
the DQ’s should be controlled by using DQMU and DQML to prevent bus contention. The output is
A burst read operation can be interrupted by a new read of the same or opposite bank. M5M4V4S40CTP
A burst read operation can be interrupted by a write to the same or opposite bank. For this operation,
Command
Command
DQMU
DQML
CLK
A0-7
A8
BA
CLK
A0-7
A8
BA
DQ
Q
D
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Read
READ
Yi
0
0
Yi
0
0
Read Interrupted by Write (BL=4, CL=3)
READ
Read Interrupted by Read (BL=4, CL=3)
Yj
0
0
MITSUBISHI ELECTRIC
READ
Qai0
Qai0
M5M4V4S40CTP-12, -15
Yk
0
1
DQMU/DQML control
Qaj0
Write
Daj0
Qaj1 Qbk0 Qbk1
Yj
0
0
READ
Daj1
Yl
0
0
Daj2
Write control
Qbk2
Daj3
Qal0
MITSUBISHI LSIs
Qal1 Qal2 Qal3
18