m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 12

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

mode register stores this data until the next MRS command. An MRS command can only be issued when
both banks are idle. After tRSC from an MRS operation, the SDRAM is ready for new commands.
from damage and malfunctions.
1. Apply power and start the clock, CLK. Attempt to maintain CKE high, DQMU/DQML high and NOP
conditions on the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500µs.
3. Issue precharge commands for all banks (PRE or PREA).
4. After all banks reach an idle state and after the row the precharge time (tRP) issue 8 or more auto-refresh
commands.
5. Finally, issue a mode register set (MRS) command to initialize the mode register.
After tRSC from the MRS command, the SDRAM will be in an idle state and ready for normal operations.
SDRAM (Rev. 0.3)
POWER ON SEQUENCE
MODE REGISTER
Feb ‘97 Preliminary
Burst Length, Burst Type, and /CAS Latency can be programmed by setting the mode register (MRS). The
Before starting normal operations, the following power on sequence is necessary to prevent the SDRAM
OPCODE
LATENCY
0 0
0 1
1 0
1 1
OP
MODE
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
OPCODE 0
BA A8 A7
Burst read / Burst write
Burst read / Single write
0 0 0
0 0 1
0 1 0
0 1 1
1 X X
CL
R
R
/CAS LATENCY
A6
LTMODE
MITSUBISHI ELECTRIC
R
R
1
2
3
A5 A4
M5M4V4S40CTP-12, -15
A3 A2 A1 A0
BT
BURST
TYPE
BL
LENGTH
BURST
1
0
R is Reserved for Future Use
F.P. = Full Page (256)
SEQUENTIAL
INTERLEAVED
BA, A8 -A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
CLK
/CS
/RAS
/CAS
/WE
BT= 0 BT= 1
MITSUBISHI LSIs
F.P.
1
2
4
8
R
R
R
1
2
4
8
R
R
R
R
V
12